Mahmut Yilmaz

ORCID

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 7

Top Venues

VTS

IEEE Des. Test

J. Electron. Test.

IEEE Trans. Very Large Scale Integr. Syst.

Duke University, Durham, NC, USA (PHD)

Education History

Duke University, Durham, NC, USA

PHD

Publications

Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento
NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links. IEEE Des. Test 40 (4) (2023)
Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas M. Satheesh, Kuo Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST). VTS (2022)
Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. VTS (2022)
Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang
Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms. VTS (2019)
Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha
Dynamic docking architecture for concurrent testing and peak power reduction. VTS (2016)
Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian
Advanced test methodology for complex SoCs. ITC (2016)
Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn
Flexible scan interface architecture for complex SoCs. VTS (2016)
Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects. IEEE Trans. Very Large Scale Integr. Syst. 21 (6) (2013)
Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults. J. Electron. Test. 29 (1) (2013)
Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization. Asian Test Symposium (2012)
Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor
Critical Fault-Based Pattern Generation for Screening SDDs. ETS (2011)
Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty
A Metric to Target Small-Delay Defects in Industrial Circuits. IEEE Des. Test Comput. 28 (2) (2011)
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. ITC (2010)
Ke Peng, Jason Thibodeau, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
A novel hybrid method for SDD pattern grading and selection. VTS (2010)
Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection. Asian Test Symposium (2010)
Sandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng, Mohammad Tehranipoor
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. Asian Test Symposium (2010)
Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, Kanwaldeep Sobti, Dwight Elvey, Jeff Fitzgerald, Grady Giles, Wei-Yu Chen
The scan-DFT features of AMD's next-generation microprocessor core. ITC (2010)
Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty
High-quality pattern selection for screening small-delay defects considering process variations and crosstalk. DATE (2010)
Mahmut Yilmaz, Krishnendu Chakrabarty
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects. DATE (2009)
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
Test-Pattern Grading and Pattern Selection for Small-Delay Defects. VTS (2008)
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects. ITC (2008)
Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. ICCD (2007)
Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin
Lazy Error Detection for Microprocessor Functional Units. DFT (2007)
Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev
Applying architectural vulnerability Analysis to hard faults in the microprocessor. SIGMETRICS/Performance (2006)
Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin
Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. ITC (2006)

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Publication Activity (10 Years)

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Mahmut Yilmaz