Bonita Bhaskaran

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 11

Top Topics

Integrated Circuit

Special Session

Top Venues

Publications

Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren
ChipNeMo: Domain-Adapted LLMs for Chip Design. CoRR (2023)
Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas M. Satheesh, Kuo Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST). VTS (2022)
Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang
Observation Point Insertion Using Deep Learning. ICCAD (2022)
Saurabh Gupta, Bonita Bhaskaran, Shantanu Sarangi, Ayub Abdollahian, Jennifer Dworak
A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift. IEEE Des. Test 37 (4) (2020)
Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn
An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. ITC (2019)
Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang
Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms. VTS (2019)
Saurabh Gupta, Bonita Bhaskaran, Shantanu Sarangi, Ayub Abdollahian, Jennifer Dworak
A Novel Graph Coloring Based Solution for Low-Power Scan Shift. VTS (2019)
Bonita Bhaskaran, Sailendra Chadalavada, Shantanu Sarangi, Nithin Valentine, Venkat Abilash Reddy Nerallapally, Ayub Abdollahian
At-speed capture global noise reduction & low-power memory test architecture. VTS (2017)
Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian
Advanced test methodology for complex SoCs. ITC (2016)
Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur
Test method and scheme for low-power validation in modern SOC integrated circuits. VTS (2016)
Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani
A programmable method for low-power scan shift in SoC integrated circuits. VTS (2016)
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, Scott C. Smith
Automated energy calculation and estimation for delay-insensitive digital circuits. Microelectron. J. 38 (10-11) (2007)
Venkat Satagopan, Bonita Bhaskaran, Waleed K. Al-Assadi, Scott C. Smith, Sindhu Kakarla
DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15 (10) (2007)
Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith
High-Speed Energy Estimation for Delay-Insensitive Circuits. CDES (2005)
Bonita Bhaskaran, Venkat Satagopan, Waleed K. Al-Assadi, Scott C. Smith
Implementation of Design For Test for Asynchronous NCL Designs. CDES (2005)
Waleed K. Al-Assadi, Pavankumar Chandrasekhar, Bonita Bhaskaran
Fault Modeling and Testability of CMOS Domino Circuits. CDES (2005)