At-speed capture global noise reduction & low-power memory test architecture.
Bonita BhaskaranSailendra ChadalavadaShantanu SarangiNithin ValentineVenkat Abilash Reddy NerallapallyAyub AbdollahianPublished in: VTS (2017)
Keyphrases
- low power
- noise reduction
- high speed
- vlsi architecture
- power dissipation
- power consumption
- low cost
- signal to noise ratio
- nm technology
- real time
- edge preserving
- cmos technology
- mixed signal
- edge detection
- logic circuits
- median filter
- single chip
- memory access
- noise level
- associative memory
- vlsi circuits
- noisy environments
- signal processor
- low power consumption
- power reduction
- analog to digital converter
- computer vision
- hearing aids
- speech enhancement
- data flow
- image processing
- gate array