Shantanu Sarangi

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 12

Top Topics

Vlsi Architecture

Special Session

Power Reduction

Top Venues

Publications

Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento
NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links. IEEE Des. Test 40 (4) (2023)
Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas M. Satheesh, Kuo Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST). VTS (2022)
Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. VTS (2022)
Saurabh Gupta, Bonita Bhaskaran, Shantanu Sarangi, Ayub Abdollahian, Jennifer Dworak
A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift. IEEE Des. Test 37 (4) (2020)
Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn
An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. ITC (2019)
Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang
Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms. VTS (2019)
Saurabh Gupta, Bonita Bhaskaran, Shantanu Sarangi, Ayub Abdollahian, Jennifer Dworak
A Novel Graph Coloring Based Solution for Low-Power Scan Shift. VTS (2019)
Milind Sonawane, Venkat Abilash Reddy Nerallapally, Alex Hsu, Shantanu Sarangi
Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) Latency. VTS (2019)
Bonita Bhaskaran, Sailendra Chadalavada, Shantanu Sarangi, Nithin Valentine, Venkat Abilash Reddy Nerallapally, Ayub Abdollahian
At-speed capture global noise reduction & low-power memory test architecture. VTS (2017)
Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha
Dynamic docking architecture for concurrent testing and peak power reduction. VTS (2016)
Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian
Advanced test methodology for complex SoCs. ITC (2016)
Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn
Flexible scan interface architecture for complex SoCs. VTS (2016)
Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu
A clock-gating based capture power droop reduction methodology for at-speed scan testing. DATE (2011)