Karthikeyan Natarajan

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 10

Top Topics

Parallel Implementations

Manufacturing Process

Power Reduction

Gigabit Ethernet

Top Venues

Publications

Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal
Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O. IEEE Des. Test 40 (4) (2023)
Khader S. Abdel-Hafez, Michael Dsouza, Likith Kumar Manchukonda, Elddie Tsai, Karthikeyan Natarajan, Ting-Pu Tai, Wenhao Hsueh, Smith Lai
Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs. ITC (2022)
Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal
Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/O. VTS (2022)
Likith Kumar Manchukonda, Karthikeyan Natarajan, Manish Arora
Power Aware Test. ETS (2022)
Amit Pandey, Brendan Tully, Karthikeyan Natarajan
High Speed IO Access for Test forms the foundation for Silicon Lifecycle Management. ITC (2022)
Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu
High Performance Graph Convolutional Networks with Applications in Testability Analysis. DAC (2019)
Karthikeyan Natarajan, Nitin Chandrachoodan
Lossless Parallel Implementation of a Turbo Decoder on GPU. HiPC (2018)
Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha
Dynamic docking architecture for concurrent testing and peak power reduction. VTS (2016)
Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani
A programmable method for low-power scan shift in SoC integrated circuits. VTS (2016)
Karthikeyan Natarajan, Nitin Chandrachoodan
Non-uniform DFT implementation for channel simulations in GPU. NCC (2015)
Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu
Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. VTS (2011)