Kaushik Narayanun

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 7

Top Topics

Optimization Method

Integrated Circuit

Top Venues

Publications

Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento
NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links. IEEE Des. Test 40 (4) (2023)
Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. VTS (2022)
Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang
Observation Point Insertion Using Deep Learning. ICCAD (2022)
Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn
An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. ITC (2019)
Zipeng Li, Jonathon E. Colburn, Vinod Pagalone, Kaushik Narayanun, Krishnendu Chakrabarty
Test-cost optimization in a scan-compression architecture using support-vector regression. VTS (2017)
Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur
Test method and scheme for low-power validation in modern SOC integrated circuits. VTS (2016)
Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani
A programmable method for low-power scan shift in SoC integrated circuits. VTS (2016)