A clock-gating based capture power droop reduction methodology for at-speed scan testing.

Bo Yang Amit Sanghani Shantanu Sarangi Chunsheng Liu

Published in: DATE (2011)

Keyphrases

power reduction
power consumption
clock gating
power dissipation
low power
high speed
power saving
design methodology
power management
energy efficiency
fine grained
test cases
computer vision
data center
case study