Scott C. Smith

Publication Activity (10 Years)

Years Active: 2001-2023
Publications (10 Years): 24

Top Topics

Power Transformers

Verification Method

Asynchronous Circuits

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Danylo Khodosevych, Alexander C. Bodoh, Ashiq A. Sakib, Scott C. Smith
Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits. IEEE Access 11 (2023)
Hritom Das, Ali Ahmad Haidous, Scott C. Smith, Na Gong
Approximate Memory for Low-Power Video Applications. IEEE Access 11 (2023)
Brett Sparkman, Scott C. Smith, Jia Di
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism. J. Electron. Test. 38 (3) (2022)
Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith, Nimish Mathure
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits. IET Comput. Digit. Tech. 16 (5-6) (2022)
Jingyan Fu, Zhiheng Liao, Jianqing Liu, Scott C. Smith, Jinhui Wang
Memristor-Based Variation-Enabled Differentially Private Learning Systems for Edge Computing in IoT. IEEE Internet Things J. 8 (12) (2021)
Hritom Das, Ali Ahmad Haidous, Scott C. Smith, Na Gong
Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation. IEEE Trans. Very Large Scale Integr. Syst. 29 (10) (2021)
BoHyun Ahn, Taesic Kim, Scott C. Smith, Young-Woo Youn, Myung-Hyo Ryu
Security Threat Modeling for Power Transformers in Cyber-Physical Environments. ISGT (2021)
Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith
Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits. MWSCAS (2020)
Nauman Jalil, Scott C. Smith
Further Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit. MWSCAS (2020)
Brett Sparkman, Scott C. Smith, Jia Di
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits. VTS (2020)
Ashiq A. Sakib, Scott C. Smith
Implementation of Static NCL Threshold Gates Using Emerging CNTFET Technology. ICECS (2020)
Nauman Jalil, Scott C. Smith, Roger Green
Performance optimization of rotation-tolerant Viola-Jones-based blackbird detection. J. Real Time Image Process. 17 (3) (2020)
Sahibzada Muhammad Ali, Muhammad Jawad, Muhammad Usman Shahid Khan, Kashif Bilal, Jacob Glower, Scott C. Smith, Samee U. Khan, Keqin Li, Albert Y. Zomaya
An Ancillary Services Model for Data Centers and Power Systems. IEEE Trans. Cloud Comput. 8 (4) (2020)
Ashiq A. Sakib, Abir A. Akib, Scott C. Smith
Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice. MWSCAS (2020)
Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith
Formal Verification of Completion-Completeness for NCL Circuits. MWSCAS (2020)
Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith
Hardware Trojan Design and Detection in Asynchronous NCL Circuits. ICECS (2020)
Mousam Hossain, Ashiq A. Sakib, Sudarshan K. Srinivasan, Scott C. Smith
An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits. ISCAS (2019)
Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan
Formal Modeling and Verification of PCHB Asynchronous Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27 (12) (2019)
Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan
An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits. MWSCAS (2018)
Paul Rogers, Rajesh Kavasseri, Scott C. Smith
An FPGA-in-the-loop approach for HDL motor controller verification. ReConFig (2017)
Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan
Formal modeling and verification for pre-charge half buffer gates and circuits. MWSCAS (2017)
Nasim Soufizadeh-Balaneji, Scott C. Smith
Analysis and design of CMOS resettable C-elements. MWSCAS (2017)
Paul Rogers, Rajesh Kavasseri, Scott C. Smith
An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors. ReConFig (2016)
Farhad Alibeygi Parsan, Scott C. Smith, Waleed K. Al-Assadi
Design for Testability of Sleep Convention Logic. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Farhad Alibeygi Parsan, J. Zhao, Scott C. Smith
SCL design of a pipelined 8051 ALU. MWSCAS (2014)
Farhad Alibeygi Parsan, Waleed K. Al-Assadi, Scott C. Smith
Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Vidura Wijayasekara, Sudarshan K. Srinivasan, Scott C. Smith
Equivalence verification for NULL Convention Logic (NCL) circuits. ICCD (2014)
Parviz Palangpour, Scott C. Smith
Sleep Convention Logic using partially slept function blocks. MWSCAS (2013)
Pragadesh Varadharajan, Waleed K. Al-Assadi, Shabab F. Alam, Scott C. Smith
Quantum-dot cellular automaton of asynchronous Null Convention Logic multiplier design. MWSCAS (2013)
Washington Cilio, Michael Linder, Chris Porter, Jia Di, Dale R. Thompson, Scott C. Smith
Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic. Microelectron. J. 44 (3) (2013)
Farhad Alibeygi Parsan, Scott C. Smith
CMOS implementation of static threshold gates with hysteresis: A new approach. VLSI-SoC (2012)
Robert B. Reese, Scott C. Smith, Mitchell A. Thornton
Uncle - An RTL Approach to Asynchronous Design. ASYNC (2012)
Farhad Alibeygi Parsan, Scott C. Smith
CMOS Implementation of Threshold Gates with Hysteresis. VLSI-SoC (Selected Papers) (2012)
Farhad Alibeygi Parsan, Scott C. Smith
CMOS implementation comparison of NCL gates. MWSCAS (2012)
Scott C. Smith, Waleed K. Al-Assadi, Jia Di
Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum. IEEE Trans. Educ. 53 (3) (2010)
Jingxian Wu, Scott C. Smith
Integrated software-hardware design for ultra-low power infrastructure monitoring. ITSC (2009)
Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia Di
Delay-Insensitive Ternary Logic. CDES (2009)
Parviz Palangpour, Ganesh K. Venayagamoorthy, Scott C. Smith
Particle Swarm Optimization: A Hardware Implementation. CDES (2009)
Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith
Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. 3DIC (2009)
Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, Scott C. Smith
Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power. J. Low Power Electron. 4 (3) (2008)
Scott C. Smith
Design of a logic element for implementing an asynchronous FPGA. FPGA (2007)
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, Scott C. Smith
Automated energy calculation and estimation for delay-insensitive digital circuits. Microelectron. J. 38 (10-11) (2007)
Ganesh K. Venayagamoorthy, Scott C. Smith, Gaurav Singhal
Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits. Eng. Appl. Artif. Intell. 20 (2) (2007)
Scott C. Smith
Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15 (6) (2007)
Venkat Satagopan, Bonita Bhaskaran, Waleed K. Al-Assadi, Scott C. Smith, Sindhu Kakarla
DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15 (10) (2007)
Scott C. Smith
Speedup of NULL convention digital circuits using NULL cycle reduction. J. Syst. Archit. 52 (7) (2006)
Anshul Singh, Scott C. Smith
Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. CDES (2005)
Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith
High-Speed Energy Estimation for Delay-Insensitive Circuits. CDES (2005)
Bonita Bhaskaran, Venkat Satagopan, Waleed K. Al-Assadi, Scott C. Smith
Implementation of Design For Test for Asynchronous NCL Designs. CDES (2005)
Scott C. Smith
Development of a large word-width high-speed asynchronous multiply and accumulate unit. Integr. 39 (1) (2005)
Scott C. Smith
Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput. ESA/VLSI (2004)
Scott C. Smith
Design of a NULL Convention Self-Timed Divider. ESA/VLSI (2004)
Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, Dennis Ferguson, D. Lamb
Optimization of NULL convention self-timed circuits. Integr. 37 (3) (2004)
Scott C. Smith
Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy. VLSI (2003)
Scott C. Smith, James Fisher
On generating random systems: a gramian approach. ACC (2003)
Satish K. Bandapati, Scott C. Smith, Minsu Choi
Design and Characterization of Null Convention Self-Timed Multipliers. IEEE Des. Test Comput. 20 (6) (2003)
Satish K. Bandapati, Scott C. Smith
Design and Characterization of NULL Convention Arithmetic Logic Units. VLSI (2003)
Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, M. Hagedorn, Dennis Ferguson
NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation. J. Syst. Archit. 47 (12) (2002)
Scott C. Smith
Speedup of Self-Timed Digital Systems Using Early Completion. ISVLSI (2002)
Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, M. Hagedorn, Dennis Ferguson
Delay-insensitive gate-level pipelining. Integr. 30 (2) (2001)