Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits.

Son N. Le Sudarshan K. Srinivasan Scott C. Smith

Published in: MWSCAS (2020)

Keyphrases

high speed
asynchronous circuits
model checking
formal verification
affine invariant
primal dual
low power
circuit design
analog vlsi
case study
multiscale
pattern recognition
rough sets
face verification
delay insensitive
quantum computing