Equivalence verification for NULL Convention Logic (NCL) circuits.
Vidura WijayasekaraSudarshan K. SrinivasanScott C. SmithPublished in: ICCD (2014)
Keyphrases
- asynchronous circuits
- delay insensitive
- logic synthesis
- model checking
- digital circuits
- logic circuits
- model checker
- verification method
- formal verification
- linear time temporal logic
- chip design
- random access memory
- floating gate
- nonmonotonic logics
- formal methods
- logic programming
- temporal logic
- shift register
- tunnel diode
- fault models
- epistemic logic
- power dissipation
- circuit design
- classical logic
- multi valued
- low power