Formal Verification of Completion-Completeness for NCL Circuits.
Son N. LeSudarshan K. SrinivasanScott C. SmithPublished in: MWSCAS (2020)
Keyphrases
- formal verification
- model checking
- bounded model checking
- automated verification
- model checker
- symbolic model checking
- analog circuits
- delay insensitive
- high speed
- data quality
- logic synthesis
- digital circuits
- analog vlsi
- temporal logic
- electronic circuits
- tunnel diode
- logic circuits
- circuit design
- expert systems
- power reduction
- asynchronous circuits
- markov decision processes
- object oriented
- artificial intelligence