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Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic.

Washington CilioMichael LinderChris PorterJia DiDale R. ThompsonScott C. Smith
Published in: Microelectron. J. (2013)
Keyphrases
  • delay insensitive
  • asynchronous circuits
  • low power
  • real time
  • high speed
  • power consumption
  • machine learning
  • genetic algorithm
  • objective function
  • model checking