Daniel J. Sorin

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 30

Top Venues

Publications

Weihang Li, Andrés Goens, Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin
Determining the Minimum Number of Virtual Networks for Different Coherence Protocols. ISCA (2024)
Beyza Dabak, Major Glenn, Jingyang Liu, Alexander Buck, Siyi Yang, A. Robert Calderbank, Natalie Enright Jerger, Daniel J. Sorin
Low-Energy Line Codes for On-Chip Networks. CoRR (2024)
Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis Gavrielatos, Theo X. Olausson, Reece Carr
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. IEEE Micro 43 (4) (2023)
Filip Mazurek, Arya Tschand, Yu Wang, Miroslav Pajic, Daniel J. Sorin
Rigorous Evaluation of Computer Processors with Statistical Model Checking. MICRO (2023)
Atefeh Mehrabi, Daniel J. Sorin, Benjamin C. Lee
Spatiotemporal Strategies for Long-Term FPGA Resource Management. ISPASS (2022)
Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis Gavrielatos, Theo Olausson, Reece Carr
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. HPCA (2022)
Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin
Bayesian Optimization for Efficient Accelerator Synthesis. ACM Trans. Archit. Code Optim. 18 (1) (2021)
Daniel J. Sorin
Reconfigurable Hardware in Postsilicon Microarchitecture. Computer 54 (3) (2021)
Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Daniel J. Sorin, Benjamin C. Lee, Mike O'Connor
Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures. ISPASS (2021)
Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin
Prospector: Synthesizing Efficient Accelerators via Statistical Learning. DATE (2020)
Sean Murray, George Dimitri Konidaris, Daniel J. Sorin
Roadmap Subsampling for Changing Environments. IROS (2020)
Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin
HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols. ISCA (2020)
Samantha Archer, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin
Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory. DSN (2020)
Daniel J. Sorin
Computer Architecture for Orbital Edge Computing. Computer 53 (4) (2020)
Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin
GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors. DSN (2019)
Sean Murray, Will Floyd-Jones, George Dimitri Konidaris, Daniel J. Sorin
A Programmable Architecture for Robot Motion Planning Acceleration. ASAP (2019)
Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin
Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Daniel J. Sorin
Low-Power Content Addressable Memory. Computer 51 (3) (2018)
Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin
ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications. ISCA (2018)
Opeoluwa Matthews, Daniel J. Sorin
Architecting hierarchical coherence protocols for push-button parametric verification. MICRO (2017)
Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Derek R. Hower, Daniel J. Sorin
Jenga: Efficient Fault Tolerance for Stacked DRAM. ICCD (2017)
Daniel J. Sorin
Persistent Memory. Computer 50 (3) (2017)
Alireza Vahid, Georgios Mappouras, Daniel J. Sorin, A. Robert Calderbank
Correcting Two Deletions and Insertions in Racetrack Memory. CoRR (2017)
Sean Murray, William Floyd-Jones, Ying Qi, George Dimitri Konidaris, Daniel J. Sorin
The microarchitecture of a real-time robot motion planning accelerator. MICRO (2016)
Milo M. K. Martin, Daniel J. Sorin
Top Picks from the 2015 Computer Architecture Conferences. IEEE Micro 36 (3) (2016)
Sean Murray, Will Floyd-Jones, Ying Qi, Daniel J. Sorin, George Dimitri Konidaris
Robot Motion Planning on a Chip. Robotics: Science and Systems (2016)
Blake A. Hechtman, Andrew D. Hilton, Daniel J. Sorin
TREES: A CPU/GPU Task-Parallel Runtime with Explicit Epoch Synchronization. CoRR (2016)
Opeoluwa Matthews, Jesse D. Bingham, Daniel J. Sorin
Verifiable hierarchical protocols with network invariants on parametric systems. FMCAD (2016)
Ralph Nathan, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun
Profile-Driven Automated Mixed Precision. CoRR (2016)
Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin
Methuselah Flash: Rewriting Codes for Extra Long Storage Lifetime. DSN (2016)
Adam N. Jacobvitz, Andrew D. Hilton, Daniel J. Sorin
Multi-program benchmark definition. ISPASS (2015)
Meng Zhang, Jesse D. Bingham, John Erickson, Daniel J. Sorin
PVCoherence: Designing Flat Coherence Protocols for Scalable Verification. IEEE Micro 35 (3) (2015)
Ali Eslami, Alfredo Velasco, Alireza Vahid, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin
Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design. MEMSYS (2015)
Yaqi Zhang, Ralph Nathan, Daniel J. Sorin
Reduced Precision Checking to Detect Errors in Floating Point Arithmetic. CoRR (2015)
Ralph Nathan, Daniel J. Sorin
Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores. IEEE Comput. Archit. Lett. 14 (1) (2015)
Meng Zhang, Jesse D. Bingham, John Erickson, Daniel J. Sorin
PVCoherence: Designing flat coherence protocols for scalable verification. HPCA (2014)
Opeoluwa Matthews, Meng Zhang, Daniel J. Sorin
Scalably verifiable dynamic power management. HPCA (2014)
Ralph Nathan, Daniel J. Sorin
Nostradamus: Low-cost hardware-only error detection for processor cores. DATE (2014)
Daniel J. Sorin, Opeoluwa Matthews, Meng Zhang
Architecting Dynamic Power Management to be Formally Verifiable. DAC (2014)
Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun
Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. SC (2014)
Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun
Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point. CoRR (2013)
Blake A. Hechtman, Daniel J. Sorin
Exploring memory consistency for massively-threaded throughput-oriented processors. ISCA (2013)
Kushal Seetharam, Lance Ong-Siong Co Ting Keh, Ralph Nathan, Daniel J. Sorin
Applying Reduced Precision Arithmetic to Detect Errors in Floating Point Multiplication. PRDC (2013)
Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin
Coset coding to extend the lifetime of memory. HPCA (2013)
Blake A. Hechtman, Daniel J. Sorin
Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips. CoRR (2013)
Blake A. Hechtman, Daniel J. Sorin
Evaluating cache coherent shared virtual memory for heterogeneous multicore chips. ISPASS (2013)
Milo M. K. Martin, Mark D. Hill, Daniel J. Sorin
Why on-chip cache coherence is here to stay. Commun. ACM 55 (7) (2012)
Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin
Writing cosets of a convolutional code to increase the Lifetime of Flash memory. Allerton Conference (2012)
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin
Address Translation Aware Memory Consistency. IEEE Micro 31 (1) (2011)
Patrick J. Eibl, Albert Meixner, Daniel J. Sorin
An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2. SIGMETRICS (2011)
Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, Arijit Biswas, Xavier Vera
Architectures for online error detection and recovery in multicore processors. DATE (2011)
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin
Specifying and dynamically verifying address translation-aware memory consistency. ASPLOS (2010)
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy
UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all. HPCA (2010)
Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin
Fractal Consistency: Architecting the Memory System to Facilitate Verification. IEEE Comput. Archit. Lett. 9 (2) (2010)
Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin
Fractal Coherence: Scalably Verifiable Cache Coherence. MICRO (2010)
Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, Geert Janssen
Multicore power management: Ensuring robustness via early-stage formal verification. MEMOCODE (2009)
Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin
Dynamic power gating with quality guarantees. ISLPED (2009)
Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin
Reduced Precision Checking for a Floating Point Adder. DFT (2009)
Meng Zhang, Anita Lungu, Daniel J. Sorin
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms. DFT (2009)
Albert Meixner, Daniel J. Sorin
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. IEEE Trans. Dependable Secur. Comput. 6 (1) (2009)
Bogdan F. Romanescu, Daniel J. Sorin
Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. PACT (2008)
Fred A. Bower, Daniel J. Sorin, Landon P. Cox
The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling. IEEE Micro 28 (3) (2008)
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching. Conf. Computing Frontiers (2008)
Albert Meixner, Michael E. Bauer, Daniel J. Sorin
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. IEEE Micro 28 (1) (2008)
Albert Meixner, Daniel J. Sorin
Detouring: Translating software to circumvent hard faults in simple cores. DSN (2008)
Anita Lungu, Daniel J. Sorin
Verification-Aware Microprocessor Design. PACT (2007)
Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. ICCD (2007)
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin
VariaSim: simulating circuits and systems in the presence of process variability. SIGARCH Comput. Archit. News 35 (5) (2007)
Albert Meixner, Michael E. Bauer, Daniel J. Sorin
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. MICRO (2007)
Fred A. Bower, Daniel J. Sorin, Sule Ozev
Online diagnosis of hard faults in microprocessors. ACM Trans. Archit. Code Optim. 4 (2) (2007)
Jonathan R. Carter, Sule Ozev, Daniel J. Sorin
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown CoRR (2007)
Albert Meixner, Daniel J. Sorin
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures. HPCA (2007)
Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. PACT (2007)
Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin
Lazy Error Detection for Microprocessor Functional Units. DFT (2007)
Albert Meixner, Daniel J. Sorin
Unified microprocessor core storage. Conf. Computing Frontiers (2007)
Albert Meixner, Daniel J. Sorin
Error Detection Using Dynamic Dataflow Verification. PACT (2007)
Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin
NANA: A nano-scale active network architecture. ACM J. Emerg. Technol. Comput. Syst. 2 (1) (2006)
Nathan Sadler, Daniel J. Sorin
Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache. ICCD (2006)
Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev
Applying architectural vulnerability Analysis to hard faults in the microprocessor. SIGMETRICS/Performance (2006)
Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin
Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. ITC (2006)
Albert Meixner, Daniel J. Sorin
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. DSN (2006)
Tong Li, Alvin R. Lebeck, Daniel J. Sorin
Spin Detection Hardware for Improved Management of Multithreaded Systems. IEEE Trans. Parallel Distributed Syst. 17 (6) (2006)
Fred A. Bower, Daniel J. Sorin, Sule Ozev
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. MICRO (2005)
Jonathan R. Carter, Sule Ozev, Daniel J. Sorin
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. DATE (2005)
Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News 33 (4) (2005)
Fred A. Bower, Sule Ozev, Daniel J. Sorin
Autonomic Microprocessor Execution via Self-Repairing Arrays. IEEE Trans. Dependable Secur. Comput. 2 (4) (2005)
Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin
Self-Assembled Architectures and the Temporal Aspects of Computing. Computer 38 (1) (2005)
Tong Li, Carla Schlatter Ellis, Alvin R. Lebeck, Daniel J. Sorin
Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution. USENIX Annual Technical Conference, General Track (2005)
Albert Meixner, Daniel J. Sorin
Dynamic Verification of Sequential Consistency. ISCA (2005)
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
Using Speculation to Simplify Multiprocessor Design. IPDPS (2004)
Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin
Communication breakdown: analyzing CPU usage in commercial Web workloads. ISPASS (2004)
Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin
Tolerating Hard Faults in Microprocessor Array Structures. DSN (2004)
Daniel J. Sorin, Mark D. Hill, David A. Wood
Dynamic Verification of End-to-End Multiprocessor Invariants. DSN (2003)
Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. ISCA (2003)
Daniel J. Sorin, Jonathan Lemon, Derek L. Eager, Mary K. Vernon
Analytic Evaluation of Shared-Memory Architectures. IEEE Trans. Parallel Distributed Syst. 14 (2) (2003)
Tong Li, Alvin R. Lebeck, Daniel J. Sorin
Quantifying instruction criticality for shared memory multiprocessors. SPAA (2003)
Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, Daniel J. Sorin
Simulating a $2M Commercial Server on a $2K PC. Computer 36 (2) (2003)
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood
Bandwidth Adaptive Snooping. HPCA (2002)
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. ISCA (2002)
Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. IEEE Trans. Parallel Distributed Syst. 13 (6) (2002)

Daniel J. Sorin.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Daniel J. Sorin