SAT-based ATPG for Path Delay Faults in Sequential Circuits.
Stephan EggersglüßGörschwin FeyRolf DrechslerPublished in: ISCAS (2007)
Keyphrases
- built in self test
- fault diagnosis
- fault models
- power dissipation
- shortest path
- analog circuits
- answer set programming
- ai planning
- path length
- sat solvers
- fault detection
- high speed
- bounded model checking
- model based diagnosis
- version space
- neural network
- multicast tree
- fault model
- analog vlsi
- search algorithm
- logic synthesis
- delay insensitive
- sat encodings
- boolean satisfiability