Sybille Hellebrand

Publication Activity (10 Years)

Years Active: 1988-2024
Publications (10 Years): 24

Top Topics

Special Session

Pattern Generation

Top Venues

J. Electron. Test.

Publications

Somayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich
Workload-Aware Periodic Interconnect BIST. IEEE Des. Test 41 (4) (2024)
Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich
Vmin Testing under Variations: Defect vs. Fault Coverage. LATS (2024)
Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich
Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. ETS (2024)
Abdalrhman Badran, Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand
Approximate Communication: Balancing Performance, Power, Reliability, and Safety. ETS (2023)
Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich
Optimizing the Streaming of Sensor Data with Approximate Communication. ATS (2023)
Somayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich
Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. DSN-W (2023)
Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi-Haghi, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich
Robust Pattern Generation for Small Delay Faults Under Process Variations. ITC (2023)
Somayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich
Stress-Aware Periodic Test of Interconnects. J. Electron. Test. 37 (5) (2021)
Stefan Holst, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, Xiaoqing Wen
Logic Fault Diagnosis of Hidden Delay Defects. ITC (2020)
Alexander Sprenger, Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. DFT (2020)
Somayeh Sadeghi Kohan, Sybille Hellebrand
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. VTS (2020)
Matthias Kampmann, Michael A. Kochte, Chang Liu, Eric Schneider, Sybille Hellebrand, Hans-Joachim Wunderlich
Built-In Test for Hidden Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (10) (2019)
Alexander Sprenger, Sybille Hellebrand
Divide and Compact - Stochastic Space Compaction for Faster-than-at-Speed Test. J. Circuits Syst. Comput. 28 (Supplement-1) (2019)
Mohammad Urf Maaz, Alexander Sprenger, Sybille Hellebrand
A Hybrid Space Compactor for Adaptive X-Handling. ITC (2019)
Alexander Sprenger, Sybille Hellebrand
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. DDECS (2018)
Matthias Kampmann, Sybille Hellebrand
Design for Small Delay Test - A Simulation Study. Microelectron. Reliab. 80 (2018)
Chang Liu, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, Hans-Joachim Wunderlich
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. ATS (2018)
Sybille Hellebrand, Jörg Henkel, Anand Raghunathan, Hans-Joachim Wunderlich
Guest Editors' Introduction. IEEE Embed. Syst. Lett. 10 (1) (2018)
Jyotirmoy V. Deshmukh, Wolfgang Kunz, Hans-Joachim Wunderlich, Sybille Hellebrand
Special session on early life failures. VTS (2017)
Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken
Foreword. ETS (2017)
Matthias Kampmann, Sybille Hellebrand
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. DDECS (2017)
Matthias Kampmann, Sybille Hellebrand
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. ATS (2016)
Matthias Kampmann, Michael A. Kochte, Eric Schneider, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich
Optimized Selection of Frequencies for Faster-Than-at-Speed Test. ATS (2015)
Zhengfeng Huang, Huaguo Liang, Sybille Hellebrand
A High Performance SEU Tolerant Latch. J. Electron. Test. 31 (4) (2015)
Sybille Hellebrand, Hans-Joachim Wunderlich
SAT-based ATPG beyond stuck-at fault testing. it Inf. Technol. 56 (4) (2014)
Sybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, Hans-Joachim Wunderlich
FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects. ITC (2014)
Laura Rodríguez Gómez, Alejandro Cook, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich
Adaptive Bayesian Diagnosis of Intermittent Faults. J. Electron. Test. 30 (5) (2014)
Sybille Hellebrand
Analyzing and quantifying fault tolerance properties. LATW (2013)
Alejandro Cook, Sybille Hellebrand, Hans-Joachim Wunderlich
Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test. ETS (2012)
Alejandro Cook, Sybille Hellebrand, Michael E. Imhof, Abdullah Mumtaz, Hans-Joachim Wunderlich
Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test. LATW (2012)
Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell
Towards Variation-Aware Test Methods. ETS (2011)
Alejandro Cook, Sybille Hellebrand, Thomas Indlekofer, Hans-Joachim Wunderlich
Diagnostic Test of Robust Circuits. Asian Test Symposium (2011)
Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
Variation-aware fault modeling. Sci. China Inf. Sci. 54 (9) (2011)
Viktor Froese, Rüdiger Ibers, Sybille Hellebrand
Reusing NoC-infrastructure for test data compression. VTS (2010)
Thomas Indlekofer, Michael Schnittger, Sybille Hellebrand
Efficient test response compaction for robust BIST using parity sequences. ICCD (2010)
Marc Hunger, Sybille Hellebrand
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. DFT (2010)
Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. DSN Workshops (2010)
Sybille Hellebrand
Nano-electronic Systems (Nano-elektronische Systeme). it Inf. Technol. 52 (4) (2010)
Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
Variation-Aware Fault Modeling. Asian Test Symposium (2010)
Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker
ATPG-based grading of strong fault-secureness. IOLTS (2009)
Sybille Hellebrand, Marc Hunger
Are Robust Circuits Really Robust? DFT (2009)
Marc Hunger, Sybille Hellebrand
Verification and Analysis of Self-Checking Properties through ATPG. IOLTS (2008)
Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand
A Modular Memory BIST for Optimized Memory Repair. IOLTS (2008)
Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich
Signature Rollback - A Technique for Testing Robust Circuits. VTS (2008)
Muhammad Ali, Michael Welzl, Sven Hessler, Sybille Hellebrand
An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip. Int. J. High Perform. Syst. Archit. 1 (2) (2007)
Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. DFT (2007)
Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. ETS (2007)
Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. DDECS (2007)
Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). it Inf. Technol. 48 (5) (2006)
Philipp Öhler, Sybille Hellebrand
Low power embedded DRAMs with high quality error correcting capabilities. ETS (2005)
Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. ITC (2004)
Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand
A Hybrid Coding Strategy For Optimized Test Data Compression. ITC (2003)
Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich
A Mixed-Mode BIST Scheme Based on Folding Compression. J. Comput. Sci. Technol. 17 (2) (2002)
Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik
Efficient Online and Offline Testing of Embedded DRAMs. IEEE Trans. Computers 51 (7) (2002)
Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. J. Electron. Test. 18 (2) (2002)
Sybille Hellebrand, Huaguo Liang, Hans-Joachim Wunderlich
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. J. Electron. Test. 17 (3-4) (2001)
Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich
Two-dimensional test data compression for scan-based deterministic BIST. ITC (2001)
Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang
A mixed mode BIST scheme based on reseeding of folding counters. ITC (2000)
Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. EDCC (1999)
Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik
Error Detecting Refreshment for Embedded DRAMs. VTS (1999)
Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik
Symmetric Transparent BIST for RAMs. DATE (1999)
Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
Mixed-Mode BIST Using Embedded Processors. J. Electron. Test. 12 (1-2) (1998)
Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
Synthesizing Fast, Online-Testable Control Units. IEEE Des. Test Comput. 15 (4) (1998)
Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. DATE (1998)
Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich
Fast Self-Recovering Controllers. VTS (1998)
Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska
STARBIST: Scan Autocorrelated Random Pattern Generation. DAC (1997)
Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
Mixed-Mode BIST Using Embedded Processors. ITC (1996)
Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Trans. Computers 44 (2) (1995)
Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich
Pattern generation for a deterministic BIST scheme. ICCAD (1995)
Sybille Hellebrand, Hans-Joachim Wunderlich
Synthesis of Self-Testable Controllers. EDAC-ETC-EUROASIC (1994)
Sybille Hellebrand, Hans-Joachim Wunderlich
An efficient procedure for the synthesis of fast self-testable controller structures. ICCAD (1994)
Hans-Joachim Wunderlich, Sybille Hellebrand
The pseudoexhaustive test of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (1) (1992)
Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. ITC (1992)
Sybille Hellebrand, Hans-Joachim Wunderlich
Tools and devices supporting the pseudo-exhaustive test. EURO-DAC (1990)
Sybille Hellebrand, Hans-Joachim Wunderlich, Oliver F. Haberl
Generating pseudo-exhaustive vectors for external testing. ITC (1990)
Sybille Hellebrand, Hans-Joachim Wunderlich
The Pseudo-Exhaustive Test of Sequential Circuits. ITC (1989)
Hans-Joachim Wunderlich, Sybille Hellebrand
Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits. FTCS (1988)
Sybille Hellebrand, Hans-Joachim Wunderlich
Automatisierung des Entwurfs vollständig testbarer Schaltungen. GI Jahrestagung (2) (1988)