Jaushin Lee

Publication Activity (10 Years)

Years Active: 1991-1996
Publications (10 Years): 0

Publications

Jaushin Lee, Janak H. Patel
Hierarchical test generation under architectural level functional constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (9) (1996)
Jaushin Lee, Janak H. Patel
Architectural level test generation for microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (10) (1994)
Vivek Chickermane, Jaushin Lee, Janak H. Patel
Addressing design for testability at the architectural level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (7) (1994)
Jaushin Lee, Vivek Chickermane, Janak H. Patel
Impact of high level functional constraints on testability. VTS (1993)
Jaushin Lee, Janak H. Patel
Testability analysis based on structural and behavioral information. VTS (1993)
Jaushin Lee, Janak H. Patel
An architectural level test generator based on nonlinear equation solving. J. Electron. Test. 4 (2) (1993)
Vivek Chickermane, Jaushin Lee, Janak H. Patel
Design for Testability Using Architectural Descriptions. ITC (1992)
Jaushin Lee, Janak H. Patel
An Instruction Sequence Assembling Methodology for Testing Microprocessors. ITC (1992)
Vivek Chickermane, Jaushin Lee, Janak H. Patel
A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD (1992)
Jaushin Lee, Janak H. Patel
Hierarchical Test Generation under Intensive Global Functional Constraints. DAC (1992)
Jaushin Lee, Janak H. Patel
A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. ICCAD (1991)
Jaushin Lee, Janak H. Patel
ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. ITC (1991)
Jaushin Lee, Janak H. Patel
An Architectural Level Test Generator for a Hierarchical Design Environment. FTCS (1991)