Min-Jer Wang

Publication Activity (10 Years)

Years Active: 2008-2020
Publications (10 Years): 12

Top Topics

Cmos Technology

Diagnostic Problem Solving

Top Venues

Publications

Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC-Asia (2020)
Mincent Lee, Cheng-Tse Lu, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill. ITC-Asia (2020)
Chia-Heng Tsai, Chi-Chang Lai, Hao Chen, Min-Jer Wang
Novel Circuit Probing for Tiny Inductor. ITC-Asia (2020)
Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC (2020)
Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang
High Quality Test Methodology for Highly Reliable Devices. ITC (2019)
Tang-Jung Chiu, Yu-Lun Tseng, Yen-Cheng Lin, Yi-Chen Wang, Hung-Chih Lin, Min-Jer Wang
Testing-for-manufacturing (TFM) for ultra-thin IPD on InFO. ITC-Asia (2017)
Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test 34 (3) (2017)
Hao Chen, Hung-Chih Lin, Min-Jer Wang
Fan-out wafer level chip scale package testing. ITC-Asia (2017)
Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers 66 (8) (2017)
Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC (2016)
Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test 33 (2) (2016)
Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers 65 (3) (2016)
Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. CICC (2015)
Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Wafer Level Chip Scale Package copper pillar probing. ITC (2014)
Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. IEEE Des. Test 31 (4) (2014)
Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee
/3D ICs. VLSI-DAT (2014)
Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. IEEE J. Solid State Circuits 49 (4) (2014)
Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Redundancy architectures for channel-based 3D DRAM yield improvement. ITC (2014)
Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. CICC (2014)
Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen
A novel DFT architecture for 3DIC test, diagnosis and repair. VLSI-DAT (2014)
Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC (2014)
Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang
A 4-GHz universal high-frequency on-chip testing platform for IP validation. VTS (2014)
Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC (2013)
Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin
3D-IC interconnect test, diagnosis, and repair. VTS (2013)
Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong
per MB. CICC (2013)
Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch. ITC (2013)
Peter Kuoyuan Hsu, Yukit Tang, Derek Tao, Ming-Chieh Huang, Min-Jer Wang, C. H. Wu, Quincy Lee
A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS. VLSIC (2012)
Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang
A memory yield improvement scheme combining built-in self-repair and error correction codes. ITC (2012)
Sergey Romanovsky, Atul Katoch, Arun Achyuthan, C. O'Connell, Sreedhar Natarajan, C. Huang, Chuan-Yu Wu, Min-Jer Wang, C. J. Wang, P. Chen, R. Hsieh
A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS. ISSCC (2008)