A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS.
Ming-Zhang KuoHenry HsiehSang H. DhongPing-Lin YangCheng-Chung LinRyan TsengKevin HuangMin-Jer WangWei HwangPublished in: CICC (2014)