Wafer Level Chip Scale Package copper pillar probing.

Hao Chen Hung-Chih Lin Ching-Nen Peng Min-Jer Wang

Published in: ITC (2014)

Keyphrases

low cost
high speed
higher level
small scale
integrated circuit
data sets
case study
high level
image features
computer simulation
parallel processing
levels of abstraction
massively parallel
printed circuit boards
single chip
high bandwidth