Chun-Chuan Chi

Publication Activity (10 Years)

Years Active: 2009-2014
Publications (10 Years): 0

Top Topics

Design Considerations

Defect Detection

Medical Diagnostic

Top Venues

J. Electron. Test.

Publications

Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. IEEE Des. Test 31 (4) (2014)
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin
3D-IC interconnect test, diagnosis, and repair. VTS (2013)
Erik Jan Marinissen, Chun-Chuan Chi, Mario Konijnenburg, Jouke Verbree
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper. J. Electron. Test. 28 (1) (2012)
Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin
3D-IC BISR for stacked memories using cross-die spares. VLSI-DAT (2012)
Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC (2011)
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC (2011)
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium (2011)
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
DfT Architecture for 3D-SICs with Multiple Towers. ETS (2011)
Erik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario Konijnenburg
3D DfT architecture for pre-bond and post-bond testing. 3DIC (2010)
Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li
A low-cost and scalable test architecture for multi-core chips. ETS (2010)
Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu
Test Integration for SOC Supporting Very Low-Cost Testers. Asian Test Symposium (2009)