A low-cost and scalable test architecture for multi-core chips.

Chun-Chuan Chi Cheng-Wen Wu Jin-Fu Li

Published in: ETS (2010)

Keyphrases

low cost
real time
software architecture
lightweight
management system
high speed
multi processor
information systems
low power
highly efficient
event driven
single chip
test cases
neural network
digital camera
statistical tests
database