Mincent Lee

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 10

Top Topics

Processor Array

Diagnostic Problem Solving

Top Venues

Publications

Pai-Yu Tan, Chih-Hsuan Tung, Cheng-Wen Wu, Mincent Lee, Gordon Liao
A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. VLSI-DAT (2022)
Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC-Asia (2020)
Mincent Lee, Cheng-Tse Lu, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill. ITC-Asia (2020)
Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC (2020)
Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang
High Quality Test Methodology for Highly Reliable Devices. ITC (2019)
Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test 34 (3) (2017)
Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers 66 (8) (2017)
Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC (2016)
Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test 33 (2) (2016)
Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers 65 (3) (2016)
Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Redundancy architectures for channel-based 3D DRAM yield improvement. ITC (2014)
Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen
A novel DFT architecture for 3DIC test, diagnosis and repair. VLSI-DAT (2014)
Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. Asian Test Symposium (2013)
Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
A Memory Failure Pattern Analyzer for memory diagnosis and repair. VTS (2012)
Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu
Cost modeling and analysis for interposer-based three-dimensional IC. VTS (2012)
Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang
A memory yield improvement scheme combining built-in self-repair and error correction codes. ITC (2012)
Mincent Lee, Li-Ming Denq, Cheng-Wen Wu
A Memory Built-In Self-Repair Scheme Based on Configurable Spares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (6) (2011)