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Haruki Mori
ORCID
Publication Activity (10 Years)
Years Active: 2015-2023
Publications (10 Years): 14
Top Topics
Deep Learning
Low Power
Dynamic Random Access Memory
Nm Technology
Top Venues
ICECS
ISSCC
MLSP
IEEE Trans. Circuits Syst. I Regul. Pap.
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Publications
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Haruki Mori
,
Wei-Chang Zhao
,
Cheng-En Lee
,
Chia-Fu Lee
,
Yu-Hao Hsu
,
Chao-Kai Chuang
,
Takeshi Hashizume
,
Hao-Chun Tung
,
Yao-Yi Liu
,
Shin-Rung Wu
,
Kerem Akarvardar
,
Tan-Li Chou
,
Hidehiro Fujiwara
,
Yih Wang
,
Yu-Der Chih
,
Yen-Huei Chen
,
Hung-Jen Liao
,
Tsung-Yung Jonathan Chang
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.
ISSCC
(2023)
Hidehiro Fujiwara
,
Haruki Mori
,
Wei-Chang Zhao
,
Mei-Chen Chuang
,
Rawan Naous
,
Chao-Kai Chuang
,
Takeshi Hashizume
,
Dar Sun
,
Chia-Fu Lee
,
Kerem Akarvardar
,
Saman Adham
,
Tan-Li Chou
,
Mahmut Ersin Sinangil
,
Yih Wang
,
Yu-Der Chih
,
Yen-Huei Chen
,
Hung-Jen Liao
,
Tsung-Yung Jonathan Chang
Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.
ISSCC
(2022)
Chia-Fu Lee
,
Cheng-Han Lu
,
Cheng-En Lee
,
Haruki Mori
,
Hidehiro Fujiwara
,
Yi-Chun Shih
,
Tan-Li Chou
,
Yu-Der Chih
,
Tsung-Yung Jonathan Chang
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications.
VLSI Technology and Circuits
(2022)
Yu-Der Chih
,
Po-Hao Lee
,
Hidehiro Fujiwara
,
Yi-Chun Shih
,
Chia-Fu Lee
,
Rawan Naous
,
Yu-Lin Chen
,
Chieh-Pu Lo
,
Cheng-Han Lu
,
Haruki Mori
,
Wei-Cheng Zhao
,
Dar Sun
,
Mahmut E. Sinangil
,
Yen-Huei Chen
,
Tan-Li Chou
,
Kerem Akarvardar
,
Hung-Jen Liao
,
Yih Wang
,
Meng-Fan Chang
,
Tsung-Yung Jonathan Chang
All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.
ISSCC
(2021)
Haruki Mori
,
Tomoki Nakagawa
,
Yuki Kitahara
,
Yuta Kawamoto
,
Kenta Takagi
,
Shusuke Yoshimoto
,
Shintaro Izumi
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
(4) (2019)
Yuki Miyauchi
,
Haruki Mori
,
Tetsuya Youkawa
,
Kazuki Yamada
,
Shintato Izumi
,
Masahiko Yoshimoto
,
Hiroshi Kawaguchi
,
Atsuki Inoue
Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth.
ICECS
(2018)
Tetsuya Youkawa
,
Haruki Mori
,
Yuki Miyauchi
,
Kazuki Yamada
,
Shintaro Izumi
,
Masahiko Yoshimoto
,
Hiroshi Kawaguchi
Delayed Weight Update for Faster Convergence in Data-Parallel Deep Learning.
GlobalSIP
(2018)
Haruki Mori
,
Shintaro Izumi
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning.
ICECS
(2018)
Kazuki Yamada
,
Haruki Mori
,
Tetsuya Youkawa
,
Yuki Miyauchi
,
Shintaro Izumi
,
Masahiko Yoshimoto
,
Hiroshi Kawaguchi
Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning.
SiPS
(2018)
Haruki Mori
,
Tetsuya Youkawa
,
Shintaro Izumi
,
Masahiko Yoshimoto
,
Hiroshi Kawaguchi
,
Atsuki Inoue
A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning.
MLSP
(2017)
Haruki Mori
,
Yohei Umeki
,
Shusuke Yoshimoto
,
Shintaro Izumi
,
Koji Nii
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor.
IEICE Trans. Electron.
(8) (2016)
Haruki Mori
,
Tomoki Nakagawa
,
Yuki Kitahara
,
Yuta Kawamoto
,
Kenta Takagi
,
Shusuke Yoshimoto
,
Shintaro Izumi
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology.
ICECS
(2016)
Tomoki Nakagawa
,
Shintaro Izumi
,
Koji Yanagida
,
Yuki Kitahara
,
Shusuke Yoshimoto
,
Yohei Umeki
,
Haruki Mori
,
Hiroto Kitahara
,
Hiroshi Kawaguchi
,
Hiromitsu Kimura
,
Kyoji Marumoto
,
Takaaki Fuchikami
,
Yoshikazu Fujimori
,
Masahiko Yoshimoto
A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques.
ISCAS
(2015)
Haruki Mori
,
Tomoki Nakagawa
,
Yuki Kitahara
,
Yuta Kawamoto
,
Kenta Takagi
,
Shusuke Yoshimoto
,
Shintaro Izumi
,
Koji Nii
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.
CICC
(2015)