Brian Crafton

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 26

Top Topics

Efficient Processing

Target Tracking

Top Venues

Publications

Xiaoyu Sun, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (4) (2024)
Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. IEEE J. Solid State Circuits 59 (1) (2024)
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC (2024)
Ashwin Sanjay Lele, Muya Chang, Samuel Spetalnick, Yan Fang, Brian Crafton, Shota Konno, Arijit Raychowdhury
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. ISCAS (2023)
Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. VLSI Technology and Circuits (2023)
Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. ISSCC (2023)
Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Arijit Raychowdhury, Yan Fang
Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem. DAC (2023)
Brian Crafton, Connor Talley, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury
Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory. ISCAS (2022)
Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. ISSCC (2022)
Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
Improving compute in-memory ECC reliability with successive correction. DAC (2022)
Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. ISSCC (2022)
Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. A-SSCC (2021)
Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury
Merged Logic and Memory Fabrics for AI Workloads. ASP-DAC (2021)
Brian Crafton, Arijit Raychowdhury, Sung Kyu Lim
Automatic Generation of Translators for Packet-Based and Emerging Protocols. ISQED (2021)
Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury
Statistical Optimization of Compute In-Memory Performance Under Device Variation. ISLPED (2021)
Brian Crafton, Samuel Spetalnick, Yan Fang, Arijit Raychowdhury
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads. IEEE Des. Test 38 (1) (2021)
Brian Crafton, Andrew Paredes, Evan Gebhardt, Arijit Raychowdhury
Hardware-Algorithm Co-Design Enabling Efficient Event-based Object Detection. AICAS (2021)
Foroozan Karimzadeh, Ningyuan Cao, Brian Crafton, Justin Romberg, Arijit Raychowdhury
A Hardware-Friendly Approach Towards Sparse Neural Networks Based on LFSR-Generated Pseudo-Random Sequences. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics. VLSI-SoC (Selected Papers) (2020)
Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury
Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics. CoRR (2020)
Foroozan Karimzadeh, Ningyuan Cao, Brian Crafton, Justin Romberg, Arijit Raychowdhury
Hardware-Aware Pruning of DNNs using LFSR-Generated Pseudo-Random Indices. ISCAS (2020)
Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury
Counting Cards: Exploiting Weight and Variance Distributions for Robust Compute In-Memory. CoRR (2020)
Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. VLSI-SOC (2020)
Brian Crafton, Abhinav Parihar, Evan Gebhardt, Arijit Raychowdhury
Direct Feedback Alignment with Sparse Connections for Local Learning. CoRR (2019)
Brian Crafton, Matt West, Padip Basnet, Eric Vogel, Arijit Raychowdhury
Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment. ISLPED (2019)
Foroozan Karimzadeh, Ningyuan Cao, Brian Crafton, Justin Romberg, Arijit Raychowdhury
Hardware-aware Pruning of DNNs using LFSR-Generated Pseudo-Random Indices. CoRR (2019)