Sigang Ryu

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 9

Top Topics

Robot Localization

Clock Frequency

Transfer Function

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

Publications

Sigang Ryu, Jaeha Kim, Arijit Raychowdhury
Fractionally-Spaced Equalizers as Clock and Data Recovery Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (7) (2024)
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC (2024)
Sigang Ryu, Adou Sangbone Assoa, Shota Konno, Arijit Raychowdhury
A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications. VLSI Technology and Circuits (2023)
Adou Sangbone Assoa, Ashwin Bhat, Sigang Ryu, Arijit Raychowdhury
A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems. ACM Great Lakes Symposium on VLSI (2023)
Sigang Ryu, Chan Young Park, Wooryeol Kim, Seuk Son, Jaeha Kim
A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Sigang Ryu, Seuk Son, Jaeha Kim
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Seuk Son, Sigang Ryu, Hwanseok Yeo, Jaeha Kim
A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery. IEEE J. Solid State Circuits 54 (10) (2019)
Seuk Son, Hwanseok Yeo, Sigang Ryu, Jaeha Kim
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery. A-SSCC (2018)
Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son, Jaeha Kim
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications. ISSCC (2016)
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function. IEEE J. Solid State Circuits 49 (8) (2014)
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim
A 9.2-GHz digital phase-locked loop with peaking-free transfer function. CICC (2013)
Jaeha Kim, Sigang Ryu, Byoung-Joo Yoo, Hanseok Kim, Yunju Choi, Deog-Kyoon Jeong
A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs. ISCAS (2012)