Muya Chang

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 30

Top Topics

Corneal Reflections

Array Processor

Combinatorial Optimization Problems

Signal Reconstruction

Top Venues

IEEE J. Solid State Circuits

Publications

Steven Davis, Jianbo Liu, Boyang Cheng, Muya Chang, Ningyuan Cao
In-Situ Privacy via Mixed-Signal Perturbation and Hardware-Secure Data Reversibility. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (6) (2024)
Kaushik Bhattacharyya, Minxiang Gong, Muya Chang, Xin Zhang, Arijit Raychowdhury
A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC. ISCAS (2024)
Nealson Li, Muya Chang, Arijit Raychowdhury
E-Gaze: Gaze Estimation With Event Camera. IEEE Trans. Pattern Anal. Mach. Intell. 46 (7) (2024)
Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. IEEE J. Solid State Circuits 59 (1) (2024)
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC (2024)
Ashwin Sanjay Lele, Muya Chang, Samuel Spetalnick, Yan Fang, Brian Crafton, Shota Konno, Arijit Raychowdhury
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. ISCAS (2023)
Mustafa Fayez Ali, Indranil Chakraborty, Sakshi Choudhary, Muya Chang, Dong Eun Kim, Arijit Raychowdhury, Kaushik Roy
A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads. CICC (2023)
Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. VLSI Technology and Circuits (2023)
Jianbo Liu, Boyang Cheng, Pengyu Zeng, Steven Davis, Muya Chang, Ningyuan Cao
Privacy-by-Sensing with Time-domain Differentially-Private Compressed Sensing. DATE (2023)
Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. ISSCC (2023)
Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Arijit Raychowdhury, Yan Fang
Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem. DAC (2023)
Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. ISSCC (2022)
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. IEEE J. Solid State Circuits 57 (1) (2022)
Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. ISSCC (2022)
Ningyuan Cao, Baibhab Chatterjee, Jianbo Liu, Boyang Cheng, Minxiang Gong, Muya Chang, Shreyas Sen, Arijit Raychowdhury
A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller. IEEE J. Solid State Circuits 57 (8) (2022)
Muya Chang, Xunzhao Yin, Zoltán Toroczkai, Xiaobo Hu, Arijit Raychowdhury
An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems. CICC (2022)
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. IEEE J. Solid State Circuits 57 (3) (2022)
Ningyuan Cao, Jianbo Liu, Boyang Cheng, Muya Chang
Stochastic Mixed-Signal Circuit Design for In-Sensor Privacy. ICCAD (2022)
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. ISSCC (2021)
Minxiang Gong, Ningyuan Cao, Muya Chang, Arijit Raychowdhury
A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. CICC (2021)
Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong-Hyun Seo, Muya Chang, Avinash Varna, Harish K. Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. IEEE J. Solid State Circuits 56 (1) (2021)
Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong-Hyun Seo, Muya Chang, Avinash Varna, Harish Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation. ISSCC (2020)
Ningyuan Cao, Muya Chang, Arijit Raychowdhury
A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics. IEEE J. Solid State Circuits 55 (1) (2020)
Muya Chang, Li-Hsiang Lin, Justin Romberg, Arijit Raychowdhury
OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers. IEEE J. Solid State Circuits 55 (3) (2020)
Ningyuan Cao, Baibhab Chatterjee, Minxiang Gong, Muya Chang, Shreyas Sen, Arijit Raychowdhury
A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller. VLSI Circuits (2020)
Muya Chang, Li-Hsiang Lin, Justin Romberg, Arijit Raychowdhury
Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations. CICC (2019)
Ningyuan Cao, Muya Chang, Arijit Raychowdhury
A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics. ISSCC (2019)
Muya Chang, Samantak Gangopadhyay, Tomer Hamam, Justin Romberg, Arijit Raychowdhury
Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture. ICASSP (2019)
Insik Yoon, Muya Chang, Kai Ni, Matthew Jerry, Samantak Gangopadhyay, Gus Henry Smith, Tomer Hamam, Vijayakrishan Narayanan, Justin Romberg, Shih-Lien Lu, Suman Datta, Arijit Raychowdhury
A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations. DRC (2018)