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Hwanseok Yeo
ORCID
Publication Activity (10 Years)
Years Active: 2013-2019
Publications (10 Years): 3
Top Topics
Multipath
Transfer Function
Image Enhancement
Clock Gating
Top Venues
IEEE J. Solid State Circuits
A-SSCC
ISSCC
CICC
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Publications
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Seuk Son
,
Sigang Ryu
,
Hwanseok Yeo
,
Jaeha Kim
A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery.
IEEE J. Solid State Circuits
54 (10) (2019)
Seuk Son
,
Hwanseok Yeo
,
Sigang Ryu
,
Jaeha Kim
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery.
A-SSCC
(2018)
Hwanseok Yeo
,
Sigang Ryu
,
Yoontaek Lee
,
Seuk Son
,
Jaeha Kim
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications.
ISSCC
(2016)
Sigang Ryu
,
Hwanseok Yeo
,
Yoontaek Lee
,
Seuk Son
,
Jaeha Kim
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function.
IEEE J. Solid State Circuits
49 (8) (2014)
Sigang Ryu
,
Hwanseok Yeo
,
Yoontaek Lee
,
Seuk Son
,
Jaeha Kim
A 9.2-GHz digital phase-locked loop with peaking-free transfer function.
CICC
(2013)