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Seuk Son
ORCID
Publication Activity (10 Years)
Years Active: 2012-2021
Publications (10 Years): 5
Top Topics
Transfer Function
Image Enhancement
Clock Gating
Dynamic Range
Top Venues
IEEE J. Solid State Circuits
IEEE Trans. Circuits Syst. I Regul. Pap.
CICC
A-SSCC
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Publications
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Sigang Ryu
,
Chan Young Park
,
Wooryeol Kim
,
Seuk Son
,
Jaeha Kim
A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC.
IEEE Trans. Circuits Syst. I Regul. Pap.
68 (7) (2021)
Sigang Ryu
,
Seuk Son
,
Jaeha Kim
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops.
IEEE Trans. Circuits Syst. I Regul. Pap.
(3) (2019)
Seuk Son
,
Sigang Ryu
,
Hwanseok Yeo
,
Jaeha Kim
A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery.
IEEE J. Solid State Circuits
54 (10) (2019)
Seuk Son
,
Hwanseok Yeo
,
Sigang Ryu
,
Jaeha Kim
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery.
A-SSCC
(2018)
Hwanseok Yeo
,
Sigang Ryu
,
Yoontaek Lee
,
Seuk Son
,
Jaeha Kim
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications.
ISSCC
(2016)
Sigang Ryu
,
Hwanseok Yeo
,
Yoontaek Lee
,
Seuk Son
,
Jaeha Kim
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function.
IEEE J. Solid State Circuits
49 (8) (2014)
Seuk Son
,
Hanseok Kim
,
Myeong-Jae Park
,
Kyung-Hoon Kim
,
E.-Hung Chen
,
Brian S. Leibowitz
,
Jaeha Kim
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm.
IEEE J. Solid State Circuits
48 (11) (2013)
Sigang Ryu
,
Hwanseok Yeo
,
Yoontaek Lee
,
Seuk Son
,
Jaeha Kim
A 9.2-GHz digital phase-locked loop with peaking-free transfer function.
CICC
(2013)
Jihyun Ryoo
,
Seuk Son
,
Jaeha Kim
Design of low-power high-radix switch fabric with partially-activated input and output lines.
ISOCC
(2012)
Myeong-Jae Park
,
Hanseok Kim
,
Seuk Son
,
Jaeha Kim
A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection.
CICC
(2012)