Mahmut E. Sinangil

ORCID

Publication Activity (10 Years)

Years Active: 2008-2021
Publications (10 Years): 9

Top Venues

IEEE J. Solid State Circuits

ISSCC

ICIP

A-SSCC

Massachusetts Institute of Technology, Cambridge, MA, USA (PHD)

Education History

Massachusetts Institute of Technology, Cambridge, MA, USA

PHD

Publications

Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang
All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. ISSCC (2021)
Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. IEEE J. Solid State Circuits 56 (1) (2021)
Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. ISSCC (2020)
Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Mahmut E. Sinangil, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester
A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination. IEEE J. Solid State Circuits 54 (1) (2019)
Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell. IEEE J. Solid State Circuits 54 (4) (2019)
Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang
A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology. VLSI Circuits (2018)
Chuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan
Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics. IEEE J. Solid State Circuits 52 (10) (2017)
Mahmut E. Sinangil, John W. Poulton, Matthew R. Fojtik, Thomas H. Greer, Stephen G. Tell, Andreas J. Gotterba, Jesse Wang, Jason Golbus, Brian Zimmer, William J. Dally, C. Thomas Gray
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. IEEE J. Solid State Circuits 51 (2) (2016)
Chuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan
Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics. A-SSCC (2016)
Mahmut E. Sinangil, Anantha P. Chandrakasan
Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9× Lower Energy/Access. IEEE J. Solid State Circuits 49 (1) (2014)
Yildiz Sinangil, Sabrina M. Neuman, Mahmut E. Sinangil, Nathan Ickes, George Bezerra, Eric Lau, Jason E. Miller, Henry Hoffmann, Srinivas Devadas, Anantha P. Chandrakasan
A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation. VLSIC (2014)
Arijit Banerjee, Mahmut E. Sinangil, John W. Poulton, C. Thomas Gray, Benton H. Calhoun
A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. ISQED (2014)
Mahmut E. Sinangil, Anantha P. Chandrakasan
An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access. ISSCC (2013)
Mahmut E. Sinangil, Vivienne Sze, Minhua Zhou, Anantha P. Chandrakasan
Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard. IEEE J. Sel. Top. Signal Process. 7 (6) (2013)
Henry Hoffmann, Jim Holt, George Kurian, Eric Lau, Martina Maggio, Jason E. Miller, Sabrina M. Neuman, Mahmut E. Sinangil, Yildiz Sinangil, Anant Agarwal, Anantha P. Chandrakasan, Srinivas Devadas
Self-aware computing in the Angstrom processor. DAC (2012)
Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko
A 28 nm 0.6 V Low Power DSP for Mobile Applications. IEEE J. Solid State Circuits 47 (1) (2012)
Mahmut E. Sinangil, Anantha P. Chandrakasan, Vivienne Sze, Minhua Zhou
Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard. ICIP (2012)
Mahmut E. Sinangil, Marcus Yip, Masood Qazi, Rahul Rithe, Joyce Kwong, Anantha P. Chandrakasan
Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems. IEEE Trans. Circuits Syst. II Express Briefs (9) (2012)
Mahmut E. Sinangil, Anantha P. Chandrakasan, Vivienne Sze, Minhua Zhou
Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine. ICIP (2012)
Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko
A 28nm 0.6V low-power DSP for mobile applications. ISSCC (2011)
Mahmut E. Sinangil, Hugh Mair, Anantha P. Chandrakasan
A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V. ISSCC (2011)
Masood Qazi, Mahmut E. Sinangil, Anantha P. Chandrakasan
Challenges and Directions for Low-Voltage SRAM. IEEE Des. Test Comput. 28 (1) (2011)
Anantha P. Chandrakasan, Denis C. Daly, Daniel F. Finchelstein, Joyce Kwong, Yogesh K. Ramadass, Mahmut E. Sinangil, Vivienne Sze, Naveen Verma
Technologies for Ultradynamic Voltage Scaling. Proc. IEEE 98 (2) (2010)
Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan
A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS. IEEE J. Solid State Circuits 44 (11) (2009)
Vivienne Sze, Daniel F. Finchelstein, Mahmut E. Sinangil, Anantha P. Chandrakasan
A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder. IEEE J. Solid State Circuits 44 (11) (2009)
Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan
A reconfigurable 65nm SRAM achieving voltage scalability from 0.25-1.2V and performance scalability from 20kHz-200MHz. ESSCIRC (2008)

Mahmut E. Sinangil.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Mahmut E. Sinangil