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A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.

Qing DongZhehong WangJongyup LimYiqun ZhangMahmut E. SinangilYi-Chun ShihYu-Der ChihTsung-Yung Jonathan ChangDavid T. BlaauwDennis Sylvester
Published in: IEEE J. Solid State Circuits (2019)
Keyphrases
  • design considerations
  • database
  • data sets
  • databases
  • neural network
  • operating system
  • times faster
  • parallel processing