Login / Signup
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell.
Mahmut E. Sinangil
Yen-Ting Lin
Hung-Jen Liao
Jonathan Chang
Published in:
IEEE J. Solid State Circuits (2019)
Keyphrases
</>
low voltage
cmos technology
random access memory
design considerations
high speed
data management
power consumption
low power
image processing
design methodology
power reduction