A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology.
Mahmut E. SinangilYen-Ting LinHung-Jen LiaoJonathan ChangPublished in: VLSI Circuits (2018)
Keyphrases
- cmos technology
- low voltage
- random access memory
- low power
- design considerations
- power consumption
- high speed
- case study
- parallel processing
- design process
- nm technology
- cost effective
- signal processing
- digital signal processing
- power dissipation
- low cost
- learning environment
- real time
- embedded dram
- dynamic random access memory