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Arijit Banerjee
ORCID
Publication Activity (10 Years)
Years Active: 2014-2019
Publications (10 Years): 3
Top Topics
Low Energy
Coarse Grained
Clock Gating
Deformable Objects
Top Venues
CICC
ISQED
ISLPED
VLSI Design
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Publications
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Arijit Banerjee
,
Benton H. Calhoun
A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications.
VLSI Design
(2019)
Arijit Banerjee
,
Sumanth Kamineni
,
Benton H. Calhoun
Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications.
ISLPED
(2018)
Arijit Banerjee
,
Ningxi Liu
,
Harsh N. Patel
,
Benton H. Calhoun
,
John W. Poulton
,
C. Thomas Gray
A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.
CICC
(2017)
Arijit Banerjee
,
Jacob Breiholz
,
Benton H. Calhoun
A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations.
CICC
(2015)
Arijit Banerjee
,
Mahmut E. Sinangil
,
John W. Poulton
,
C. Thomas Gray
,
Benton H. Calhoun
A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs.
ISQED
(2014)