A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation.
Mahmut E. SinangilJohn W. PoultonMatthew R. FojtikThomas H. GreerStephen G. TellAndreas J. GotterbaJesse WangJason GolbusBrian ZimmerWilliam J. DallyC. Thomas GrayPublished in: IEEE J. Solid State Circuits (2016)