Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.
Hidehiro FujiwaraHaruki MoriWei-Chang ZhaoKinshuk KhareCheng-En LeeXiaochen PengVineet JoshiChao-Kai ChuangShu-Huan HsuTakeshi HashizumeToshiaki NaganumaChen-Hung TienYao-Yi LiuYen-Chien LaiChia-Fu LeeTan-Li ChouKerem AkarvardarSaman AdhamYih WangYu-Der ChihYen-Huei ChenHung-Jen LiaoTsung-Yung Jonathan ChangPublished in: ISSCC (2024)
Keyphrases
- random access memory
- design considerations
- analog to digital converter
- level parallelism
- memory access
- embedded dram
- processing elements
- shared memory
- endpoints
- distributed processing
- management system
- master slave
- multithreading
- main memory
- low voltage
- multi processor
- associative memory
- real time
- bit parallel
- parallel hardware
- power consumption
- virtual memory
- ieee trans
- parallel implementation
- parallel architecture
- low power
- memory management
- memory hierarchy
- power reduction
- mixed signal
- parallel computers
- external memory
- sigma delta
- massively parallel
- operating system
- processing units