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A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control.

Chen-Ting KoTing-Kuei KuanRuei-Pin ShenChih-Hsien Chang
Published in: IEEE J. Solid State Circuits (2020)
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