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A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW.
Tsung-Hsien Tsai
Ruey-Bin Sheen
Chih-Hsien Chang
Robert Bogdan Staszewski
Published in:
VLSI Circuits (2018)
Keyphrases
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power consumption
high speed
user friendly
low power
power supply
charge coupled devices
frequency band
hd video
low cost
dual band
nm technology
expert systems
multiresolution
clock frequency
dielectric constant