A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process.

Wei-Bin Yang Chao-Cheng Liao Yung-Chih Liang

Published in: Microelectron. J. (2011)

Keyphrases

high speed
nm technology
database
neural network
information retrieval
data structure
signature file
bit vector
random access memory
bit vectors