A 64-MHz∼640-MHz 64-phase clock generator.

Hong-Yi Huang Jen-Chieh Liu Shi-Jia Sun Cheng-Hao Fu Kuo-Hsing Cheng

Published in: DDECS (2014)

Keyphrases

high speed
high frequency
fpga device
low power
databases
real time
neural network
information systems
power consumption
training phase