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Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture.

Yo-Hao TuJen-Chieh LiuKuo-Hsing Cheng
Published in: IEICE Trans. Electron. (2016)
Keyphrases
  • error reduction
  • classification error
  • significant improvement
  • hardware implementation
  • semi supervised
  • feature selection
  • data sets
  • iterative learning