Yo-Hao Tu

Publication Activity (10 Years)

Years Active: 2010-2021
Publications (10 Years): 9

Top Topics

Power Consumption

Compressed Sensing

Error Reduction

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IET Circuits Devices Syst.

Publications

Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng
A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications. IEEE Trans. Very Large Scale Integr. Syst. 29 (10) (2021)
Jieqiong Du, Chien-Heng Wong, Yo-Hao Tu, Wei-Han Cho, Yilei Li, Yuan Du, Po-Tsang Huang, Sheau Jiung Lee, Mau-Chung Frank Chang
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET. NOCS (2019)
Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2018)
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang
Low supply voltage and multiphase all-digital crystal-less clock generator. IET Circuits Devices Syst. 12 (6) (2018)
Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng
A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application. ISCAS (2018)
Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering. VLSI-DAT (2017)
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture. IEICE Trans. Electron. (6) (2016)
Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang
A chaotically injected timing technique for ring-based oscillators. DDECS (2016)
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. IEICE Electron. Express 13 (2) (2016)
Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang
A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. DDECS (2015)
Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang
A low supply voltage synchronous mirror delay with quadrature phase output. DDECS (2014)
Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang
A low jitter delay-locked-loop applied for DDR4. DDECS (2013)
Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng
A 3 GHz DLL-based clock generator with stuck locking protection. ICECS (2010)