Boris Hudec

Publication Activity (10 Years)

Years Active: 2015-2020
Publications (10 Years): 6

Top Topics

Defeasible Logic

Online Training

Gradient Vector

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

Sci. China Inf. Sci.

Microelectron. Reliab.

Publications

Sandeep Kaur Kingra, Vivek Parmar, Shubham Negi, Sufyan Khan, Boris Hudec, Tuo-Hung Hou, Manan Suri
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE Using OxRAM Crossbar. CoRR (2020)
Sandeep Kaur Kingra, Vivek Parmar, Shubham Negi, Sufyan Khan, Boris Hudec, Tuo-Hung Hou, Manan Suri
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar. ISCAS (2020)
Sandeep Kaur Kingra, Vivek Parmar, Che-Chia Chang, Boris Hudec, Tuo-Hung Hou, Manan Suri
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices. CoRR (2018)
Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (1) (2018)
Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse. CoRR (2017)
Boris Hudec, Chung-Wei Hsu, I-Ting Wang, Wei-Li Lai, Che-Chia Chang, Taifang Wang, Karol Fröhlich, Chia-Hua Ho, Chen-Hsi Lin, Tuo-Hung Hou
3D resistive RAM cell design for high-density storage class memory - a review. Sci. China Inf. Sci. 59 (6) (2016)
Chun-Tse Chou, Boris Hudec, Chung-Wei Hsu, Wei-Li Lai, Chih-Cheng Chang, Tuo-Hung Hou
bilayer RRAM. Microelectron. Reliab. 55 (11) (2015)