Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Pai-Yu ChenDeepak KadetotadZihan XuAbinash MohantyBinbin LinJieping YeSarma B. K. VrudhulaJae-sun SeoYu CaoShimeng YuPublished in: DATE (2015)
Keyphrases
- learning algorithm
- case study
- programmable logic
- optimal design
- vlsi implementation
- circuit design
- nm technology
- design process
- machine learning algorithms
- low cost
- cmos technology
- high speed
- optimization algorithm
- engineering design
- embedded systems
- current status
- single chip
- optimization method
- back propagation
- user interface
- optimum design
- chip design
- metal oxide semiconductor
- neural network