A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS.
Samuel LeshnerKrzysztof S. BerezowskiXiaoyin YaoGayathri ChalivendraSaurabh PatelSarma B. K. VrudhulaPublished in: ISVLSI (2010)
Keyphrases
- low power
- cmos technology
- power consumption
- low cost
- high speed
- low power consumption
- signal processor
- nm technology
- single chip
- vlsi circuits
- image sensor
- wireless transmission
- high power
- power reduction
- logic circuits
- vlsi architecture
- delay insensitive
- mixed signal
- digital signal processing
- ultra low power
- general purpose
- floating point
- power management