George A. Constantinides

ORCID

Publication Activity (10 Years)

Years Active: 1982-2024
Publications (10 Years): 140

Top Venues

Publications

Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides
Exploring FPGA designs for MX and beyond. CoRR (2024)
Samuel Coward, Theo Drane, Emiliano Morini, George A. Constantinides
Combining Power and Arithmetic Optimization via Datapath Rewriting. ARITH (2024)
Martin Langhammer, George A. Constantinides
Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap. HEART (2024)
Zixi Zhang, Cheng Zhang, Xitong Gao, Robert D. Mullins, George A. Constantinides, Yiren Zhao
Unlocking the Global Synergies in Low-Rank Adapters. CoRR (2024)
Martin Langhammer, George A. Constantinides
A Statically and Dynamically Scalable Soft GPGPU. FPGA (2024)
Yuang Chen, Cheng Zhang, Xitong Gao, Robert D. Mullins, George A. Constantinides, Yiren Zhao
Optimised Grouped-Query Attention Mechanism for Transformers. CoRR (2024)
Marta Andronic, George A. Constantinides
NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions. CoRR (2024)
Samuel Coward, Theo Drane, Emiliano Morini, George A. Constantinides
Combining Power and Arithmetic Optimization via Datapath Rewriting. CoRR (2024)
Cheng Zhang, Jianyi Cheng, George A. Constantinides, Yiren Zhao
LQER: Low-Rank Quantization Error Reconstruction for LLMs. CoRR (2024)
Martin Langhammer, George A. Constantinides
A Statically and Dynamically Scalable Soft GPGPU. CoRR (2024)
Martin Langhammer, George A. Constantinides
Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap. CoRR (2024)
Samuel Coward, Theo Drane, George A. Constantinides
ROVER: RTL Optimization via Verified E-Graph Rewriting. CoRR (2024)
Marta Andronic, George A. Constantinides
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference. CoRR (2023)
Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Milos D. Ercegovac
Multiplier Optimization via E-Graph Rewriting. CoRR (2023)
Marta Andronic, George A. Constantinides
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference. ICFPT (2023)
Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? CoRR (2023)
Benjamin Ramhorst, George A. Constantinides, Vladimir Loncar
FPGA Resource-aware Structured Pruning for Real-Time Neural Networks. CoRR (2023)
Martin Langhammer, George A. Constantinides
eGPU: A 750 MHz Class Soft GPGPU for FPGA. FPL (2023)
Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides
ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. CoRR (2023)
Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits. DSN-W (2023)
Martin Langhammer, George A. Constantinides
eGPU: A 750 MHz Class Soft GPGPU for FPGA. CoRR (2023)
Benjamin Ramhorst, Vladimir Loncar, George A. Constantinides
FPGA Resource-aware Structured Pruning for Real-Time Neural Networks. ICFPT (2023)
Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Erwei Wang, Marie Auffret, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah, James J. Davis
Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Jianyi Cheng, Estíbaliz Fraca, John Wickerson, George A. Constantinides
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets. IEEE Trans. Computers 72 (11) (2023)
Samuel Coward, George A. Constantinides, Theo Drane
Automating Constraint-Aware Datapath Optimization using E-Graphs. DAC (2023)
Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides
Datapath Verification via Word-Level E-Graph Rewriting. CoRR (2023)
Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
Enabling Binary Neural Network Training on the Edge. ACM Trans. Embed. Comput. Syst. 22 (6) (2023)
Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides
ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. FCCM (2023)
Samuel Coward, George A. Constantinides, Theo Drane
Combining E-Graphs with Abstract Interpretation. SOAP@PLDI (2023)
Ian McInerney, Eric C. Kerrigan, George A. Constantinides
Horizon-Independent Preconditioner Design for Linear Predictive Control. IEEE Trans. Autom. Control. 68 (1) (2023)
Samuel Coward, George A. Constantinides, Theo Drane
Automating Constraint-Aware Datapath Optimization using E-Graphs. CoRR (2023)
Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides
Datapath Verification via Word-Level E-Graph Rewriting. FMCAD (2023)
Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing. CF (2023)
Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? EMNLP (2023)
Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
A Parametrizable Template for Approximate Logic Synthesis. DSN-W (2023)
Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Milos D. Ercegovac
Multiplier Optimization via E-Graph Rewriting. ACSSC (2023)
Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides
POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. FPL (2022)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Xuefei He, Jianyi Cheng, George A. Constantinides
Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis. FPT (2022)
Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides
MIDAS: Mutual Information Driven Approximate Synthesis. ISVLSI (2022)
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers 71 (4) (2022)
Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed Abdelfattah
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA (2022)
Nadesh Ramanathan, George A. Constantinides, John Wickerson
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis. ACM Trans. Design Autom. Electr. Syst. 27 (4) (2022)
Jianyi Cheng, John Wickerson, George A. Constantinides
Finding and Finessing Static Islands in Dynamically Scheduled Circuits. FPGA (2022)
Samuel Coward, George A. Constantinides, Theo Drane
Automatic Datapath Optimization using E-Graphs. CoRR (2022)
Samuel Coward, George A. Constantinides, Theo Drane
Combining E-Graphs with Abstract Interpretation. CoRR (2022)
Jianyi Cheng, John Wickerson, George A. Constantinides
Dynamic C-Slow Pipelining for HLS. FCCM (2022)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson
Dynamic Inter-Block Scheduling for HLS. FPL (2022)
Samuel Coward, George A. Constantinides, Theo Drane
Abstract Interpretation on E-Graphs. CoRR (2022)
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Benjamin Biggs, Ian McInerney, Eric C. Kerrigan, George A. Constantinides
High-level Synthesis using the Julia Language. CoRR (2022)
Samuel Coward, George A. Constantinides, Theo Drane
Automatic Datapath Optimization using E-Graphs. ARITH (2022)
Jianyi Cheng, John Wickerson, George A. Constantinides
Probabilistic Scheduling in High-Level Synthesis. FCCM (2021)
Dovydas Joksas, Erwei Wang, Nikolaos Barmpatsalos, Wing H. Ng, Anthony J. Kenyon, George A. Constantinides, Adnan Mehonic
Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks. CoRR (2021)
Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
Enabling Binary Neural Network Training on the Edge. EMDL@MobiSys (2021)
George A. Constantinides, Fredrik Dahlqvist, Zvonimir Rakamaric, Rocco Salvia
Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations. CAV (2) (2021)
George A. Constantinides, Fredrik Dahlqvist, Zvonimir Rakamaric, Rocco Salvia
Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations. CoRR (2021)
Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
Enabling Binary Neural Network Training on the Edge. CoRR (2021)
Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed Abdelfattah
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR (2021)
Jianyi Cheng, John Wickerson, George A. Constantinides
Probabilistic Optimization for High-Level Synthesis. FPGA (2021)
Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides
Learning Boolean Circuits from Examples for Approximate Logic Synthesis. ASP-DAC (2021)
Jianyi Cheng, John Wickerson, George A. Constantinides
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. FPL (2021)
Nadesh Ramanathan, George A. Constantinides, John Wickerson
Global Analysis of C Concurrency in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 29 (1) (2021)
He Li, Ian McInerney, James J. Davis, George A. Constantinides
Digit Stability Inference for Iterative Methods Using Redundant Number Representation. IEEE Trans. Computers 70 (7) (2021)
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda
Approximate Logic Synthesis: A Survey. Proc. IEEE 108 (12) (2020)
Ian McInerney, Eric C. Kerrigan, George A. Constantinides
Horizon-independent Preconditioner Design for Linear Predictive Control. CoRR (2020)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA (2020)
He Li, Ian McInerney, James J. Davis, George A. Constantinides
Digit Stability Inference for Iterative Methods Using Redundant Number Representation. CoRR (2020)
Nadesh Ramanathan, George A. Constantinides, John Wickerson
Precise Pointer Analysis in High-Level Synthesis. FPL (2020)
He Li, James J. Davis, John Wickerson, George A. Constantinides
architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute. IEEE Trans. Very Large Scale Integr. Syst. 28 (2) (2020)
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. IEEE Trans. Computers 69 (12) (2020)
Fredrik Dahlqvist, Rocco Salvia, George A. Constantinides
A Probabilistic Approach to Floating-Point Arithmetic. ACSSC (2019)
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR (2019)
Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides
Automatic Software and Computing Hardware Codesign for Predictive Control. IEEE Trans. Control. Syst. Technol. 27 (5) (2019)
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA (2019)
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM (2019)
He Li, James J. Davis, John Wickerson, George A. Constantinides
ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute. CoRR (2019)
Ian McInerney, Eric C. Kerrigan, George A. Constantinides
Modeling Round-off Error in the Fast Gradient Method for Predictive Control. CDC (2019)
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR (2019)
Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR (2019)
Fredrik Dahlqvist, Rocco Salvia, George A. Constantinides
A Probabilistic Approach to Floating-Point Arithmetic. CoRR (2019)
Ian McInerney, Eric C. Kerrigan, George A. Constantinides
Bounding Computational Complexity under Cost Function Scaling in Predictive Control. CoRR (2019)
Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu
Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. FPT (2019)
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. DAC (2019)
George A. Constantinides
Rethinking Arithmetic for Deep Neural Networks. CoRR (2019)
Ameer M. S. Abdelhadi, Christos-Savvas Bouganis, George A. Constantinides
Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization. FPT (2019)
Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides
Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (4) (2019)
Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. 52 (2) (2019)
Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu
Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs. CoRR (2019)
Florian Faissole, George A. Constantinides, David Thomas
Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis. FCCM (2019)
Graeme M. Bragg, Charles Leech, Domenico Balsamo, James J. Davis, Eduardo Wächter, Geoff V. Merrett, George A. Constantinides, Bashir M. Al-Hashimi
An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems. PECCS (2018)
Georgios Chatzianastasiou, George A. Constantinides
An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics. FPL (2018)
He Li, James J. Davis, John Wickerson, George A. Constantinides
Digit Elision for Arbitrary-accuracy Iterative Computation. ARITH (2018)
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11 (1) (2018)
Nadesh Ramanathan, George A. Constantinides, John Wickerson
Concurrency-Aware Thread Scheduling for High-Level Synthesis. FCCM (2018)
Nadesh Ramanathan, John Wickerson, George A. Constantinides
Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware. IEEE Trans. Computers 67 (7) (2018)
Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
Hardware Compilation of Deep Neural Networks: An Overview. ASAP (2018)
Nicolas Brisebarre, George A. Constantinides, Milos Ercezovac, Silviu-Ioan Filip, Matei Istoan, Jean-Michel Muller
A High Throughput Polynomial and Rational Function Approximations Evaluator. ARITH (2018)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL (2018)

George A. Constantinides.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

George A. Constantinides