Andrea Suardi

Publication Activity (10 Years)

Years Active: 2008-2019
Publications (10 Years): 3

Top Topics

Computing Platform

Dc Dc Converter

Predictive Control

Error Probability

Top Venues

IEEE Trans. Control. Syst. Technol.

Publications

Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides
Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (4) (2019)
Bulat Khusainov, Eric C. Kerrigan, Andrea Suardi, George A. Constantinides
Nonlinear Predictive Control on a Heterogeneous Computing Platform. CoRR (2017)
Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides
Quantifying error: Extending static timing analysis with probabilistic transitions. DATE (2017)
Andrea Suardi, Eric C. Kerrigan, George A. Constantinides
Fast FPGA prototyping toolbox for embedded optimization. ECC (2015)
Eric C. Kerrigan, George A. Constantinides, Andrea Suardi, Andrea Picciau, Bulat Khusainov
Computer architectures to close the loop in real-time optimization. CDC (2015)
Sabato Manfredi, Andrea Suardi
Optimization-based procedure to support sensor network co-design: An application to dynamic consensus problem. MED (2014)
Edward Nicholas Hartley, Juan Luis Jerez, Andrea Suardi, Jan M. Maciejowski, Eric C. Kerrigan, George A. Constantinides
Predictive Control Using an FPGA With Application to Aircraft Control. IEEE Trans. Control. Syst. Technol. 22 (3) (2014)
Andrea Suardi, Stefano Longo, Eric C. Kerrigan, George A. Constantinides
Energy-aware MPC co-design for DC-DC converters. ECC (2013)
Andrea Abba, Antonio Manenti, Andrea Suardi, Angelo Geraci, Giancarlo Ripamonti
Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices. ERSA (2009)
Andrea Suardi, Antonio Manenti, Andrea Abba, Angelo Geraci
High-efficiency FPGA Fully-Based Implementation of the Conjugate Gradient Method. ERSA (2009)
Andrea Suardi, Antonio Manenti, Andrea Abba, Angelo Geraci
High Performance Double Precision Reduction Circuit Implementation in FPGA. ERSA (2008)