Lana Josipovic

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 30

Top Topics

Delay Insensitive

Database Machine

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Jiahui Xu, Lana Josipovic
Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing. FPGA (2024)
Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. FPGA (2024)
Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne
DynaRapid: From C to FPGA in a Few Seconds. FPGA (2024)
Hanyu Wang, Carmine Rizzi, Lana Josipovic
MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization. ICCAD (2023)
Jiahui Xu, Emmet Murphy, Jordi Cortadella, Lana Josipovic
Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. FPGA (2023)
Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. FPGA (2023)
Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
Resource Sharing in Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Jiahui Xu, Lana Josipovic
Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. ICCAD (2023)
Carmine Rizzi, Andrea Guerrieri, Lana Josipovic
An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits. DAC (2023)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic
A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. FPL (2022)
Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella
Buffer Placement and Sizing for High-Performance Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 15 (1) (2022)
Lana Josipovic, Andrea Guerrieri, Paolo Ienne
From C/C++ Code to High-Performance Dataflow Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
Resource Sharing in Dataflow Circuits. FCCM (2022)
Jürgen Becker, Lana Josipovic, Viktor K. Prasanna, Marco D. Santambrogio, Ramachandran Vaidyanathan
29th Reconfigurable Architectures Workshop (RAW 2022). IPDPS Workshops (2022)
Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. FPL (2022)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson
Dynamic Inter-Block Scheduling for HLS. FPL (2022)
Jiantao Liu, Carmine Rizzi, Lana Josipovic
Load-Store Queue Sizing for Efficient Dataflow Circuits. FPT (2022)
Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
Resource Sharing in Dataflow Circuits. FPGA (2021)
Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella
Buffer Placement and Sizing for High-Performance Dataflow Circuits. FPGA (2020)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA (2020)
Lana Josipovic, Andrea Guerrieri, Paolo Ienne
Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. FPGA (2020)
Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. FPT (2019)
Lana Josipovic, Andrea Guerrieri, Paolo Ienne
Speculative Dataflow Circuits. FPGA (2019)
Lana Josipovic, Radhika Ghosal, Paolo Ienne
Dynamically Scheduled High-level Synthesis. FPGA (2018)
Lana Josipovic, Philip Brisk, Paolo Ienne
From C to elastic circuits. ACSSC (2017)
Lana Josipovic, Philip Brisk, Paolo Ienne
An Out-of-Order Load-Store Queue for Spatial Computing. FCCM (2017)
Lana Josipovic, Philip Brisk, Paolo Ienne
An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Lana Josipovic, Nithin George, Paolo Ienne
Enriching C-based High-Level Synthesis with parallel pattern templates. FPT (2016)