Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking.
Jiahui XuEmmet MurphyJordi CortadellaLana JosipovicPublished in: FPGA (2023)
Keyphrases
- model checking
- asynchronous circuits
- temporal logic
- formal verification
- formal specification
- temporal properties
- model checker
- partial order reduction
- symbolic model checking
- finite state
- bounded model checking
- formal methods
- finite state machines
- reachability analysis
- automated verification
- computation tree logic
- epistemic logic
- pspace complete
- concurrent systems
- verification method
- data flow
- timed automata
- software engineering
- process algebra
- linear temporal logic