Paolo Ienne

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 69

Top Venues

FPGA

FPL

ACM Trans. Reconfigurable Technol. Syst.

FPT

Publications

Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. FPGA (2024)
Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne
DynaRapid: From C to FPGA in a Few Seconds. FPGA (2024)
Stefan Nikolic, Paolo Ienne
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns. ACM Trans. Reconfigurable Technol. Syst. 17 (1) (2024)
Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. FPGA (2023)
Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
Resource Sharing in Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Paolo Ienne
Introduction to the Special Section on FPGA 2022. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Stefan Nikolic, Paolo Ienne
Regularity Matters: Designing Practical FPGA Switch-Blocks. FPGA (2023)
Jovan Blanusa, Kubilay Atasu, Paolo Ienne
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles. CoRR (2023)
Jovan Blanusa, Kubilay Atasu, Paolo Ienne
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles. ACM Trans. Parallel Comput. 10 (3) (2023)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Mikhail Asiatici, Paolo Ienne
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15 (2) (2022)
Jovan Blanusa, Paolo Ienne, Kubilay Atasu
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. CoRR (2022)
Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic
A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. FPL (2022)
Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella
Buffer Placement and Sizing for High-Performance Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 15 (1) (2022)
Lana Josipovic, Andrea Guerrieri, Paolo Ienne
From C/C++ Code to High-Performance Dataflow Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
Resource Sharing in Dataflow Circuits. FCCM (2022)
Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. FPL (2022)
Stefan Nikolic, Grace Zgheib, Paolo Ienne
Detailed Placement for Dedicated LUT-Level FPGA Interconnect. ACM Trans. Reconfigurable Technol. Syst. 15 (4) (2022)
Jovan Blanusa, Paolo Ienne, Kubilay Atasu
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. SPAA (2022)
Mikhail Asiatici, Paolo Ienne
Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. ISCA (2021)
Mikhail Asiatici, Damian Maiorano, Paolo Ienne
How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System. J. Signal Process. Syst. 93 (12) (2021)
Stefan Nikolic, Francky Catthoor, Zsolt Tokei, Paolo Ienne
Global Is the New Local: FPGA Architecture at 5nm and Beyond. FPGA (2021)
Stefan Nikolic, Paolo Ienne
Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence. FPL (2021)
Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
Resource Sharing in Dataflow Circuits. FPGA (2021)
Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella
Buffer Placement and Sizing for High-Performance Dataflow Circuits. FPGA (2020)
Stefan Nikolic, Grace Zgheib, Paolo Ienne
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. FPL (2020)
Stefan Nikolic, Grace Zgheib, Paolo Ienne
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. FPGA (2020)
Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu
Many-Core Clique Enumeration with Fast Set Intersections. Proc. VLDB Endow. 13 (11) (2020)
Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu
Parallelizing Maximal Clique Enumeration on Modern Manycore Processors. IPDPS Workshops (2020)
Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA (2020)
Lana Josipovic, Andrea Guerrieri, Paolo Ienne
Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. FPGA (2020)
Mikhail Asiatici, Damian Maiorano, Paolo Ienne
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. ASAP (2020)
Anastasiia Kucherenko, Stefan Nikolic, Paolo Ienne
On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure. FPGA (2019)
Gabor Csordas, Mikhail Asiatici, Paolo Ienne
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. FPT (2019)
Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. FPT (2019)
Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne
Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips. IEEE Access 7 (2019)
Stefan Nikolic, Grace Zgheib, Paolo Ienne
Finding a Needle in the Haystack of Hardened Interconnect Patterns. FPL (2019)
Mikhail Asiatici, Paolo Ienne
Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. FPGA (2019)
Lana Josipovic, Andrea Guerrieri, Paolo Ienne
Speculative Dataflow Circuits. FPGA (2019)
Mikhail Asiatici, Paolo Ienne
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. FPL (2019)
Mikhail Asiatici, Damian Maiorano, Paolo Ienne
)(Abstract Only). FPGA (2018)
Lana Josipovic, Radhika Ghosal, Paolo Ienne
Dynamically Scheduled High-level Synthesis. FPGA (2018)
Andrea Guerrieri, Sahand Kashani-Akhavan, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne
A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing. AHS (2018)
Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne
LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). FPGA (2018)
João Vieira, Nuno Roma, Pedro Tomás, Paolo Ienne, Gabriel Falcão Paiva Fernandes
Exploiting Compute Caches for Memory Bound Vector Operations. SBAC-PAD (2018)
Lana Josipovic, Philip Brisk, Paolo Ienne
From C to elastic circuits. ACSSC (2017)
Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI (2017)
Grace Zgheib, Paolo Ienne
Evaluating FPGA clusters under wide ranges of design parameters. FPL (2017)
Lana Josipovic, Philip Brisk, Paolo Ienne
An Out-of-Order Load-Store Queue for Spatial Computing. FCCM (2017)
João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva
Design Space Exploration of LDPC Decoders Using High-Level Synthesis. IEEE Access 5 (2017)
Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5 (2017)
Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. FPGA (2017)
Lana Josipovic, Philip Brisk, Paolo Ienne
An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. DAC (2017)
Zidong Du, Shaoli Liu, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Qi Guo, Xiaobing Feng, Yunji Chen, Olivier Temam
An Accelerator for High Efficient Vision Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (2) (2017)
Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. FPGA (2016)
Lana Josipovic, Nithin George, Paolo Ienne
Enriching C-based High-Level Synthesis with parallel pattern templates. FPT (2016)
Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad
Introduction: Special Section on Architecture of Future Many Core Systems. Microprocess. Microsystems 46 (2016)
Paolo Ienne, Jean-Pierre Talpin
Guest Editorial: Special Issue on Models and Methodologies for System Design. ACM Trans. Embed. Comput. Syst. 15 (2) (2016)
Francesco Regazzoni, Paolo Ienne
Instruction Set Extensions for secure applications. DATE (2016)
Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad
Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. IEEE Trans. Computers 65 (4) (2016)
Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT (2016)
Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD (2016)
Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko
Fast hierarchical NPN classification. FPL (2016)
Wei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, Ryan Kastner
Imprecise security: quality and complexity tradeoffs for hardware information flow tracking. ICCAD (2016)
Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
Preface. FPL (2016)
Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. 24 (12) (2016)
Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne
Designing a virtual runtime for FPGA accelerators in the cloud. FPL (2016)
Grace Zgheib, Paolo Ienne
Automatic wire modeling to explore novel FPGA architectures. FPT (2016)
Xavier Jimenez, David Novo, Paolo Ienne
Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash. ACM Trans. Embed. Comput. Syst. 14 (2) (2015)
João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. FCCM (2015)
Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen, Olivier Temam
ShiDianNao: shifting vision processing closer to the sensor. ISCA (2015)
Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu
Retraining-based timing error mitigation for hardware neural networks. DATE (2015)
Panagiotis Skrimponis, Georgios Zindros, Ioannis Parnassos, Muhsen Owaida, Nikolaos Bellas, Paolo Ienne
Exploring Automatically Generated Platforms in High Performance FPGAs. PARCO (2015)
João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. FPL (2015)
Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Trans. Embed. Comput. Syst. 14 (2) (2015)
Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne
Automatic support for multi-module parallelism from computational patterns. FPL (2015)
Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne
Improved carry chain mapping for the VTR flow. FPT (2015)
Ali Galip Bayrak, Francesco Regazzoni, David Novo, Philip Brisk, François-Xavier Standaert, Paolo Ienne
Automatic Application of Power Analysis Countermeasures. IEEE Trans. Computers 64 (2) (2015)
Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne
A technology mapper for depth-constrained FPGA logic cells. FPL (2015)
Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne
FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. Haifa Verification Conference (2015)
Andrew Becker, David Novo, Paolo Ienne
SKETCHILOG: Sketching combinational circuits. DATE (2014)
David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor
Energy efficient MIMO processing: A case study of opportunistic run-time approximations. DATE (2014)
Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Walid A. Najjar, Paolo Ienne
Reconfigurable Computing. IEEE Micro 34 (1) (2014)
Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne
Revisiting and-inverter cones. FPGA (2014)
Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne
Hardware system synthesis from Domain-Specific Languages. FPL (2014)
Jing Huang, Yuanjie Huang, Olivier Temam, Paolo Ienne, Yunji Chen, Chengyong Wu
A low-cost memory interface for high-throughput accelerators. CASES (2014)
Xavier Jimenez, David Novo, Paolo Ienne
Wear unleveling: improving NAND flash lifetime by balancing page endurance. FAST (2014)
Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne
Constrained interpolation for guided logic synthesis. ICCAD (2014)
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne
Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. ACM Trans. Archit. Code Optim. 11 (2) (2014)
Yuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, Chengyong Wu
Elastic CGRAs. FPGA (2013)
Ali Galip Bayrak, Francesco Regazzoni, David Novo, Paolo Ienne
Sleuth: Automated Verification of Software Power Analysis Countermeasures. CHES (2013)
Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Nithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne
Making domain-specific hardware synthesis tools cost-efficient. FPT (2013)
Madhura Purnaprajna, Paolo Ienne
A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. FCCM (2013)
Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA (2013)
David Novo, Sara El Alaoui, Paolo Ienne
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. DATE (2013)
David Novo, I. Tzimi, Ubaid Ahmad, Paolo Ienne, Francky Catthoor
Cracking the complexity of fixed-point refinement in complex wireless systems. SiPS (2013)
Xavier Jimenez, David Novo, Paolo Ienne
Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime. DATE (2013)

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Publication Activity (10 Years)

Top Topics

Top Venues

Paolo Ienne