Mikhail Asiatici

Publication Activity (10 Years)

Years Active: 2016-2022
Publications (10 Years): 13

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Publications

Mikhail Asiatici, Paolo Ienne
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15 (2) (2022)
Mikhail Asiatici, Paolo Ienne
Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. ISCA (2021)
Mikhail Asiatici, Damian Maiorano, Paolo Ienne
How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System. J. Signal Process. Syst. 93 (12) (2021)
Mikhail Asiatici, Damian Maiorano, Paolo Ienne
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. ASAP (2020)
Gabor Csordas, Mikhail Asiatici, Paolo Ienne
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. FPT (2019)
Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne
Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips. IEEE Access 7 (2019)
Mikhail Asiatici, Paolo Ienne
Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. FPGA (2019)
Mikhail Asiatici, Paolo Ienne
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. FPL (2019)
Mikhail Asiatici, Damian Maiorano, Paolo Ienne
)(Abstract Only). FPGA (2018)
Miku J. Laakso, Simon J. Bleiker, Jessica Liljeholm, Gustaf E. Martensson, Mikhail Asiatici, Andreas C. Fischer, Goran Stemme, Thorbjorn Ebefors, Frank Niklaus
Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires. IEEE Access 6 (2018)
Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne
LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). FPGA (2018)
Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5 (2017)
Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne
Designing a virtual runtime for FPGA accelerators in the cloud. FPL (2016)